HPS - FPGA used inside block diagram file.

[Altera_Forum]

Sirs, I'm starting using Quartus II and a DE1-SOC board (CYCLONE V). I designed a peripheral in Quartus II using a block diagram file as the main file (.BFD), and several Verilog components. The peripheral works fine and now I need to export 8 32 bit registers to the HPS. I created in QSYS a module with the HPS, configured it and generated the HDL, the resulting symbol file was created and I was able to import it to the block diagram. The problem is that the system will never compile unless the HPS is the top level entity... I tried then building an example system only using QSYS and it works that way, but I cannot easily implement the whole system just using QSYS. So the question is, "is it possible to create a system with the verilog libraries and a block diagram, and later incorporate a module of the HPS to export the resulting data?". The information out there is really confusing about this. 

 Thanks!!

[Altera_Forum]

I managed to rebuild the connections of the bsf system by hand using structural verilog and using that as a top file (such as the examples in: http://zhehaomao.com/blog/fpga/2013/12/22/sockit-1.html) and it worked fine. I just cant understand why building it graphically doesn't work. It looks like it have something to do with the exported signals from the "memory" interface, I tried several combinations of assigning them with no sucess.

[Altera_Forum]

Well, just to share my experience, I managed to re-write the connections in the BFD diagram into a verilog .v structured file, and everything worked. The only thing is that you need to export the memory signals to the top of the .v module, and run the tcl memory script, such as it was explained in some tutorials. I did the same with the BDF block diagram, with no success...

[Altera_Forum]

--- Quote Start ---  Well, just to share my experience, I managed to re-write the connections in the BFD diagram into a verilog .v structured file, and everything worked. The only thing is that you need to export the memory signals to the top of the .v module, and run the tcl memory script, such as it was explained in some tutorials. I did the same with the BDF block diagram, with no success...  --- Quote End ---    Sadly I have the same problem. I haven't found any solution for this problem until now. It would be very good to have the chance to include the HPS as a block symbol, so it will be possible to get a better overview about the system.