HS_LVDS in signal tap

[Altera_Forum]

Greetings once again. I am still running into problems trying to lower the clock speed of ALTLVDS megafunction. I am trying to look at some of the clocks and this one, coming out of a startix II GX PLL is not cooporating. Here is the error I am getting. Is this another instance of "You cannot observe LVDS signals within the design in signal tap?" 

   I think the sclkout is a serdes... but am not totally sure     Error: PLL "vcs_interface_wrapper_pcie:vcs_2_dcb_wrapper_inst|vcs_2_dcb_rx:vcs_2_dcb_inst|s3_dpa_33_inputs:dpa0_inst|altlvds_rx:altlvds_rx_component|s3_dpa_33_inputs_lvds_rx:auto_generated|pll" has port SCLKOUT0 that can only feed port CLK0 on an LVDS receiver or transmitter WYSIWYG   Thanks

[Altera_Forum]

I think, the error message is rather clear and pretty self-explanatory. Signal tap can only access signals available for connection in the logic fabric. Dedicated SERDES clock signals aren't as well as serial SERDES in- and outputs aren't.