Handling negation by synthesis tools

[WaxyRakso]

Hi everyone,

I have noticed, that sometimes synthesis tools (including Quartus) use direct negation in the VQM synthesis output file:

assign Q = ~ A;

or

.dataa(!A),

It seems that this negation is not counted as additional logic utilization in the .rpt implementation summary file. The first code snippet generated:

Logic utilization (in ALMs) : 0 / 933,120 ( 0 % )

This raises the question, since negator is not implemented on the logic, how it is implemented? Is there some dedicated resource for negation like Hyper-Register for specific flip flops? Or can I use signals negations without worring about the logic resources?

In Xilinx there were LUT1/INV located in CLB for such operations.

Thanks,
Oskar

[Kenny_Tan]

Hi,

Kindly take note that it will require some time for us to investigate this.

Thanks

[RichardTanSY_Intel]

You can look through the Fitter Resources Usage summary to see which type of resources is used.

You may also open and look through the .fit.rpt for further details.

For my case, the fitter used the I/O pins and I can see the message below indicate that as well.

Info (169124): Fitter converted 5 user pins into dedicated programming pins

[WaxyRakso]

Hello!

Thank you for your response I looked into the .fit.rpt file, here is the snippet of it:

+------------------------------------------------------------------------------------------+
; Fitter Resource Usage Summary                                                            ;
+-------------------------------------------------------------+--------------------+-------+
; Resource                                                     ; Usage              ; %     ;
+-------------------------------------------------------------+--------------------+-------+
; Logic utilization (ALMs needed / total ALMs on device)      ; 0 / 933,120        ; 0 %   ;
; ALMs needed [=A-B+C]                                        ; 0                  ;       ;
;     [A] ALMs used in final placement [=a+b+c+d]             ; 0 / 933,120        ; 0 %   ;
;         [a] ALMs used for LUT logic and register circuitry  ; 0                  ;       ;
;         [b] ALMs used for LUT logic                         ; 0                  ;       ;
;         [c] ALMs used for register circuitry                ; 0                  ;       ;
;         [d] ALMs used for memory (up to half of total ALMs) ; 0                  ;       ;
;     [B] Estimate of ALMs recoverable by dense packing       ; 0 / 933,120        ; 0 %   ;
;     [C] Estimate of ALMs unavailable [=a+b+c+d]             ; 0 / 933,120        ; 0 %   ;
;         [a] Due to location constrained logic               ; 0                  ;       ;
;         [b] Due to LAB-wide signal conflicts                ; 0                  ;       ;
;         [c] Due to LAB input limits                         ; 0                  ;       ;
;         [d] Due to virtual I/Os                             ; 0                  ;       ;
;                                                             ;                    ;       ;
; Difficulty packing design                                   ; Low                ;       ;
;                                                             ;                    ;       ;
; Total LABs:  partially or completely used                   ; 0 / 93,312         ; 0 %   ;
;     -- Logic LABs                                           ; 0                  ;       ;
;     -- Memory LABs (up to half of total LABs)               ; 0                  ;       ;
;                                                             ;                    ;       ;
; Combinational ALUT usage for logic                          ; 0                  ;       ;
;     -- 8 input functions                                    ; 0                  ;       ;
;     -- 7 input functions                                    ; 0                  ;       ;
;     -- 6 input functions                                    ; 0                  ;       ;
;     -- 5 input functions                                    ; 0                  ;       ;
;     -- 4 input functions                                    ; 0                  ;       ;
;     -- <=3 input functions                                  ; 0                  ;       ;
; Combinational ALUT usage for route-throughs                 ; 0      

So, if I understand correctly, no logic resources (ALMs) were used to implement this negation?:

assign Q = ~ A;

Does that mean that I can use the negation of every bit in my project and it won't generate additional logic resources?

[ak6dn]

Logic functions in FPGAs are implemented via lookup tables that are programmed to implement the desired logic function.

So negation of any signal, input or output, basically comes for free. Just change the contents of the lookup table.

Invert bits as necessary to reflect output signal negation, or shuffle the order of entries to reflect input signal negation.

[WaxyRakso]

That's true, but only if we are talking about signals connected to LUTs, but what about, for example, signals connected to the output ports or to the register input ports? I belive there should be some additional logic to implement the negation in such cases?

[VenTingT]

Hi,

Do you mind to send us a small design to do further investigation?

Thanks.

[WaxyRakso]

Sure Here's a really small testcase (VQM file) that I've used:

module top(A, Q);
input A;
output Q;
assign Q = ~A;
endmodule

after implementation this generates 0 ALMs, as stated in my previous comments.

[RichardTanSY_Intel · Accepted solution]

From what I get from Quartus is that there is no logic resources (ALMs) were used to implement the negation. 

You may test it out by using negation on every bit in your project or bigger design and see if it generate any additional logic resources.

[RichardTanSY_Intel]

Do you have further question in regards to this case?

[RichardTanSY_Intel]

Since there are no feedback for this thread and I believed I have answered your question.

With that, I will now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

Best Regards,

Richard Tan

p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 9/10 survey.

[WaxyRakso]

Hello!

sorry for the delayed reply. Yes, your comment about no logic resources (ALMs) used to implement the negation answers my question

Thanks for your help