How can I hard-lock specific logic cells and set the interconnection manually?
For example, two LCELL cells which I want to be as close as possible to one another without changing their location between compilations?
2. Open Chip planner --> Make sure this cell is well placed
3. Project --> Generate .tcl file 'XXX_tcl_v1' (save at output_files)
4. Open generated file
5. Update the rest of the cells accordingly
6. delete unecessary line from the addign_editor
7.tools --> tcl scripts --> run
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