Can the DDR3 memory hard memory controller (Arria V) do burst lengths of 8 cycles with a 32 bit wide ram?.
The controller will do bursts of 8 cycles for a 16 bit memory (8*16=128 bits), but adding a second DRAM in simulation has not improved my memory bandwidth because the controller has scaled back to bursts to 4 cycles (4*32=128 bits), with 4 cycle gaps between them.
Any way to get the memory controller back to doing 8 cycle bursts?
Maybe it's because the Avalon bus is 128 bits and the controller doesn't know how to merge two consecutive accesses together. I see hints that there might of burst merging feature on some memory controllers, but I don't see a way to turn it on here.
