I have a working example with a trigger from the Cyclone V SoC FPGA arriving on trigger input 2 of the FPGA-CTI, mapped to CTM channel 1, mapped to trigger output 4 of the csCTI so that it appears as a timestamped event in the STM. I have two questions about the behavior:
1. The csCTI shows only two bits that go to the STM, trigger outputs 4 and 5, yet these connect to 4 bits on the STM, hwevents[1:0] and hwevents[3:2] respectively. When the FPGA cross trigger occurs, I see two hwevents stamped in the STM separated by a bit of time. For example, if I map the event to csCTI trigger output 4, I see hwevent[0] in the STM and then less than 1 second later I see hwevent[1]. I was expecting only one event. What is the meaning of both events?
2. The second event causes the processor to stop (breakpoint) in Altera DS-5. How do I enable/disable this breakpoint due to a cross-trigger event?
Thanks,
Steve
