Hard memory controller / phy startup problem on A5GX

Programmable Devices

CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

Hard memory controller / phy startup problem on A5GX

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I'm having trouble running a DDR3 controller with HMC on an Arria V GX. The IP simulates well, but on the FPGA, it

seems to hang when the Sequencer (s0) tries to write to the PHY through the AVL interface (see attached screenshot).

Hardware: Arria V GX Starter Board (5AGXFB3H4F35C5ES)

Software: Quartus 13.1

Main VHDL file of generated DDR3 controller IP is attached.

Do you have any ideas?

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