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Hi...
I need small help.. I have Encoder which has one input MTINP (3 bit/3 wire) and MTOUT (3 wire/3 bit).now i want to connect to this pins to FPGA(EP1C3 module)..if suppose i will rotate Encoder shaft then it will generate output..Now here i want to connect this output to FPGA (using VHDL)so i have made like.. MTOUT : in std_logic_vector(2 downto 0); // Output of Encoder is the input for FPGA I need this output in FPGA for further process..here i also need MTIN for some application in FPGA..But here i dont know how to define in VHDL.. MTIN : in std_logic_vector(2 downto 0); is it correct ?? ie i declared MTIN as input for FPGA coz here its my input for Encoder.. am i right or wrong ?? i dont have logic diagram or any logic circuit because i will connect my encoder pin to FPGA but i dont know how to define MTIN and what precaution do i need ?? Thanks a lot..Link Copied
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If I understood You correctly, You want to create a bidirectional port. There, You must create a tri-state buffer. It may look something like this:
Port : inout std_logic_vector (2 downto 0); And then in architecture section you must define tri-state buffer: Port <= Port_out when Out_enable = '1' else (others => 'Z'); If You want to use Port as output You must turn Out_enable signal to '1'. Otherwise it will work as input. Hope I made it clear to You :)
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