Hardware primitives giving odd behavior

[Altera_Forum]

I am a student just starting with Verilog and am trying to create a module to take all the numbers between 0 and 63 and then modulo them by three and five.  

 I am trying to do it with a pair of hardware primitives, and the modulo three works, but trying to modulo by other numbers mysteriously does not. I tried five, two, and four now and they have all given me very odd output in both the simulator and on the DE2 board I am working with.   EDIT: Removed the large output I had posted to post all the outputs and source files for the different modulos I have tried into the expanded zip file I posted below. All the different modulos I have created are just copy pastes from the Mod3 file with which I then alter the outputs.

[Altera_Forum]

Realized that I should just package the outputs in text files, also wanted to give the tables for the different modulos I have tried. Have done 2/3/4/5/10 now, and only 3 works.  

 Things I have tried as well: using only one primitive in the top level, separate inputs for the different primitives, changing the amount of time in the test bench, and re-writing the entire truth table. I get the same wrong outputs on every time regardless of what I do.

[Altera_Forum]

The in0 to in5 bit order is upside down.

[Altera_Forum]

*The "More You Know Star" goes past* 

 Thank you very much!