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AHart2
New Contributor I
1,150 Views

Hello, is there a known problem with the ethernet MACs DMA controller in the CYCLONE V SOC devices ?

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I observe the EMACS DMA controller fails to correctly update the descriptors status in DMA ring mode. What I can clearly see is that

within the rx-ring single descriptors are omitted i.e. the own biot remains set whereas the next descriptor after this is valid. In this situation the linux driver stops and the rx ring is filled until it the overrun error bit is set.

I have tried a "dirty hack" and double checked if the next descriptor holds

valid data when the current is owned by the DMA controller. My design operates with both EMACs of the SOC connected to a GMII to SGMII bridge/transceiver i.e. GMII is routed through the fpga fabric.

 

 

 

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AHart2
New Contributor I
102 Views

Dear Anand,

Dear Nooraini,

 

thank you for getting back to me and sorry for my late reply.

Meanwhile it seems that we have found the reason for the failing

DMA transfers from GMAC. The 'shared attributes override' Bit in

the L2C Cache controllers AUX_CONTROL Register must be set to

one. This can be done either via bootloader patch or by adding the

"arm,shared-override" parameter to the L2C node in the devicetree.

Otherwise the Rx Path fails after some minutes when theres high

network traffic.

 

@ Anand : Yes I was able to ping the description. I have added some debug

code to the driver to output the descriptor ring immediately when the DMA#

fails.

 

Please close this request.

 

All the best,

Andre

 

 

 

 

 

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3 Replies
Nooraini_Y_Intel
Employee
102 Views

Hi,

 

Currently I am reviewing the forum for any open questions and found this thread. I apologize that no one seems to answer this question that you posted. Since it has been a while you posted this question, I'm wondering if you have found the answer? If not, please let me know, I will try to assign someone to assist you. Thank you.

 

Regards,

Nooraini

AnandRaj_S_Intel
Employee
102 Views

Hi,

 

  1. Can you ping the connection?
  2. Is the connection data transfer successfully receive packets? and how you have checked it?
  3. how do you access the descriptor - DS5 or Linux ?

 

Best Regards,

Anand Raj Shankar

(This message was posted on behalf of Intel Corporation)

AHart2
New Contributor I
103 Views

Dear Anand,

Dear Nooraini,

 

thank you for getting back to me and sorry for my late reply.

Meanwhile it seems that we have found the reason for the failing

DMA transfers from GMAC. The 'shared attributes override' Bit in

the L2C Cache controllers AUX_CONTROL Register must be set to

one. This can be done either via bootloader patch or by adding the

"arm,shared-override" parameter to the L2C node in the devicetree.

Otherwise the Rx Path fails after some minutes when theres high

network traffic.

 

@ Anand : Yes I was able to ping the description. I have added some debug

code to the driver to output the descriptor ring immediately when the DMA#

fails.

 

Please close this request.

 

All the best,

Andre

 

 

 

 

 

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