Help: Cyclone 10CL025YE144 implementing LVDS receiver and what pins I can do this on and how>

[LouLoulou]

Dear All,

I hope this message finds you well. I am currently exploring the implementation of LVDS directly on an FPGA, particularly on a Cyclone 10 LP device. My aim is to interface it with an LVDS device that outputs a simple 1 pulse per second signal. It's worth noting that I don't require SERDES functionality for this task, as the 1 pulse per second data is not encoded – it can be viewed as 'normal' on/off binary.

To initiate this integration within Quartus, I began by creating a basic schematic in my top-level design file. I simply placed an input pin and an output pin, connecting them together to create a straightforward test device. Upon compilation, the process was successful without any issues.

Moving on to the pin-planner, I located the input pin and adjusted its IO standard to LVDS. As expected, the pin-planner automatically generated 1pps(n), considering the requirement for two pins in LVDS. However, I encountered a surprising limitation at this stage. Despite the flexibility expected, I found that I could only choose from around 10 possible pin locations. This left me somewhat perplexed, as it appears that only a select few of the I/O pins on the 10CL025 are useable as  LVDS receivers. This seems somewhat restrictive to me.

I would greatly appreciate any insights or guidance on this matter. Am I overlooking something fundamental, or perhaps approaching this process incorrectly?

Additionally, if anyone could direct me to a beginner's guide or instructional video on the utilization of LVDS in the Cyclone 10 series of FPGA parts, it would be immensely helpful.

Thank you sincerely for your assistance.

Warm regards,

Lou

[FvM]

Your device has maximal 18 LVDS pin pairs available, as listed in Cyclone 10 LP overview and device handbook. Probably not all IO banks of your design holding LVDS pins have 2.5V supply, thus the actual selection can be less.

[LouLoulou]

Sorry, I’m in idiot I replied to myself… i meant to do this here

Thank you for the information. Can you point me to a PDF file that explains the emulated LvDS pins versus the hard LVDS pins? I was under the impression that any open could be an emulated LVDS pair but I don’t think that’s the case. Can someone please help me understand this? I’ve been struggling to find relevant documentation.

[LouLoulou]

Thank you for the information. Can you point me to a PDF file that explains the emulated LvDS pins versus the hard LVDS pins? I was under the impression that any open could be an emulated LVDS pair but I don’t think that’s the case. Can someone please help me understand this? I’ve been struggling to find relevant documentation.

[FvM]

The difference is explained in device handbook, it matters only for LVDS TX. True LVDS RX function is available at all LVDS pairs.

[AqidAyman_Intel]

Hi,

As mentioned by @FvM, the Cyclone® 10 LP devices support true input buffers for LVDS I/O standard on the top, bottom, and right I/O banks. For the output buffers for emulated LVDS transmitters with external resistors are only supported on the top and bottom I/O banks.

For more information, refer to this documentation:

https://www.intel.com/content/www/us/en/docs/programmable/683777/current/lvds-i-o-standard-in-devices.html

Regards,

Aqid

[AqidAyman_Intel]

Hi,

Is there any more help needed on this issue?

Regards,

Aqid

[AqidAyman_Intel]

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