Help Me!!!

Altera_Forum · ‎04-19-2011

(Quartus 9.1)

I need help I get: Error (10170): Verilog HDL syntax error at multiplicador_3b.v(7) near text "begin"; expecting a description.

module multiplicador_3b(P5, P4, P3, P2, P1, P0,A2, A1, A0 , B2, B1, B0);

input A2, A1, A0 , B2, B1, B0;

output P5, P4, P3, P2, P1, P0;

wire s1,s2,s3,s4,s5,s6,s7,s8,s9,s10,s11,s12,s13,s14,s15,s16,s17,s18,s19,s20,s21,s22,s23,s24,s25,s26,s27,s28,s29,s30,s31,s32,s33,s34,s35,s36,s37,s38,s39,s40,s41;

always @ (P5, P4, P3, P2, P1, P0, A2, A1, A0 , B2, B1, B0);

endmodule

begin

s1 = (B0 & A0);

P0 = s1;

s2 = (B0 & A1);

s3 = (A0 & B1);

s4 = "0";

s5 = (s3 ^ s2);

s6 = (s5 ^ s4);

P1 = s6;

s7 = (s5 & s4);

s8 = (s3 & s2);

s9 = (s7 | s8);

s10 = (B1 & A1);

s11 = (B0 & A2);

s12 = (s10 ^ s11);

s13 = (s12 ^ s9);

s14 = (s12 & s9);

s15 = (s10 & s11);

s16 = (s14 | s15);

s17 = (A2 & B1);

s18 = (s17 ^ B1);

s19 = (s18 ^ s16);

s20 = (s17 & B1);

s21 = (s18 & s16);

s22 = (s20 | s21);

s23 = (A0 & B2);

s24 = "0";

s25 = (s23 ^ s13);

s26 = (s25 ^ s24);

P2 = s26;

s27 = (s23 & s13);

s28 = (s25 & s24);

s29 = (s27 | s28);

s30 = (B2 & A1);

s31 = (s30 ^ s19);

s32 = (s31 ^ s29);

P3 = s32;

s33 = (s31 & s29);

s34 = (s30 & s19);

s35 = (s33 & s34);

s36 = (A2 & B2);

s37 = (s36 ^ s22);

s38 = (s37 ^ s35);

P4 = s38;

s39 = (s37 & s35);

s40 = (s36 & s22);

s41 = (s39 | s40);

P5 = s41;

end

Altera_Forum · ‎04-19-2011

It should look like this.