Help on VHDL

[Altera_Forum]

Just want to design a mod-12 counter counting from 0 to 12, but when I use the following code, it always set q as 0 to 7 instead of 0 to 11 (Under QSim simulator). 

====================================== Library ieee; Use ieee.std_logic_1164.all; Entity CounterTest is  port (cp, reset: in std_logic;  q: buffer integer range 0 to 64); end CounterTest ;  Architecture logicfunction of CounterTest is begin  process (reset, cp, q)  begin   if((reset = '0') OR (q > 11)) Then  q <= 0;  elsif (cp'Event AND cp='1') Then  q <= q + 1;  end if;   end process;  end logicfunction;  ======================================  But if I change the following line in process from: "if((n_rd = '0') OR (q > 11)) Then" to  "if((n_rd = '0') OR (q >= 12)) Then"  or   "if((n_rd = '0') OR (q = 12)) Then"  Then it works fine under QSim simulator. Have not tried on real FPGA yet though.   Is there any thing wrong or I missed something?  Thanks.

[Altera_Forum]

Rewrite the process this way: 

 process (reset, cp, q)  begin   if (reset = '0')   q <= 0;  elsif (cp'Event AND cp='1') Then  if (q > 11) Then  q <= 0;  else  q <= q + 1;  endif;  end if;  end process;  Otherwise the q>11 condition would be synthesized with combinatorial logic and it will lead to impredictable behaviour on real hardware, since q bits don't switch at the same time. For example, from 7 (binary 0111) to 8 (1000) you can have a transitional status like 1111 or 1101, which is >11 and would reset your counter.

[Altera_Forum]

Thanks a lot. that is really the problem. I got the idea.  

     --- Quote Start ---  Rewrite the process this way:  process (reset, cp, q)  begin   if (reset = '0')   q <= 0;  elsif (cp'Event AND cp='1') Then  if (q > 11) Then  q <= 0;  else  q <= q + 1;  endif;  end if;  end process;  Otherwise the q>11 condition would be synthesized with combinatorial logic and it will lead to impredictable behaviour on real hardware, since q bits don't switch at the same time. For example, from 7 (binary 0111) to 8 (1000) you can have a transitional status like 1111 or 1101, which is >11 and would reset your counter.  --- Quote End ---