Community
cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Valued Contributor III
744 Views

Help with PLL settings (cannot achieve a particular frequency)

I cannot seem to use a PLL to generate a particular frequency, and wondered if someone could please tell me what I am doing wrong. The PLL settings I give to Quartus are simply 

 

.reference_clock_frequency("50.000000 MHz"), 

.number_of_clocks(1), 

.output_clock_frequency0("170987637 Hz") 

 

The reason I think it should be able to synthesise the specified frequency is that the PLL can start with my 50MHz reference clock, and divide it by 9. Then the PFD runs at 5.5555556Hz, within the 5-325MHz range for my Stratix V 5SGXEA7N2F45C2. Multiplying this by 277 gives 1.53GHz, again in the supposedly legal range of 600-1600MHz for Fvco. Dividing this by another factor of 9 gives 170987637Hz if rounding down to integers during the calculation, or 170987654.3Hz without rounding. I am using the direct mode. 

 

I notice the megawizard that comes with Quartus 16.1.2 says it can approximate both frequencies by 170.138888 (without asking about the target family, let alone the speedgrade?). I have no idea why it cannot get closer. 

 

One thing I might be completely misunderstanding is whether I need the fractional mode. As far as I can tell from the documentation, I would need to enable that mode if I wanted a fractional M. Since mine is an integer within 1-511, I should be able to get by with the normal integer mode? 

 

These are the errors Quartus gives me. I have tried searching the knowledge base without finding anything relevant. I don't know where the 300MHz-800MHz range it refers to comes from. There does not seem to be any mention of that range on page 39 of the data sheet I am using (https://www.altera.com/en_us/pdfs/literature/hb/stratix-v/stx5_53001.pdf): 

 

Error: The PLL output clock frequency is currently outside of the 

Fvco device limits for the device speed grade of '2_H2'. The 

'output_clock_frequency' is '1538.888888 MHz' and the 

'pll_vco_div' is '2' on 

'something:top|altera_pll:CLK50_....' 

Line: 749 Info: "300.0 MHz to 800.0 MHz" is a legal range 

 

Error (11802): Can't fit design in device. Modify your design to 

reduce resources, or choose a larger device. The Intel FPGA 

Knowledge Database contains many articles with specific details 

on how to resolve this error. Visit the Knowledge Database at 

https://www.altera.com/support/support-resources/knowledge-base/search.html 

and search for this specific error message number. 

 

I would be very grateful if someone could please tell me what constraint I am violating, and why Quartus and the data sheet disagree if it really is the Fvco (i.e. why Quartus says it should be 300-800MHz and the data sheet thinks it can be 600-1600MHz).  

 

Sorry if I missed something obvious, and many thanks.
0 Kudos