Help with modelsim

[Altera_Forum]

Hi guys! 

 I'm having trouble simulating in modelsim. My code is below;  library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;   -- Begin entity declaration for "uppgift_vhdl_2b"-- entity test_vga is --Begin port declaration--  port (  -- Reset and clock 50 MHZ--   RESET_N, CLOCK_50 : in std_logic;  --Commmand-switches--  KEY : in std_logic_vector (2 downto 0);  --Colours (Blue/Red/Green) 8bit each--  VGA_R,VGA_G,VGA_B : out std_logic_vector (7 downto 0);  --No color,outside writing area--   VGA_BLANK_N,VGA_SYNC_N : out std_logic;  --Sync signals Horizontal/vertical, VGA clock--  VGA_HS,VGA_VS,VGA_CLK : out std_logic );   --End entity-- end entity test_vga;   --Begin architecture-- architecture vga of test_vga is     type hv_type is --Horizental/Vertical type record  H: INTEGER range 0 to 799;  V: INTEGER range 0 to 524;   end record;       signal counter_int : hv_type; signal CLK_25MHZ : std_logic;   begin   VGA_CLK<=CLK_25MHZ;       process_clock_25mhz : process(CLOCK_50) begin  if rising_edge(CLOCK_50) then  CLK_25MHZ<= not CLK_25MHZ;    end if;--end rising_edge (clock_50)--   end process;--end process_clock_25mhz--        --Sync process--  process_sync_screen : process(CLK_25MHZ)  begin    if rising_edge(CLK_25MHZ) then  if RESET_N ='0' then    counter_int.h <= 0;  counter_int.v <=0;    --Every output gets a starting value--   VGA_HS <= '1';  VGA_VS <= '1';  VGA_BLANK_N <= '1';  VGA_SYNC_N <= '0';  VGA_R <=(others =>'0');  VGA_G <=(others =>'0');  VGA_B <=(others =>'0');  else       -- Clock out RGB Pixel Row Data Horizontal Sync--  -- ------------------------------------__________--------  -- 0 639 659 755 799  if counter_int.h >= 799 then  counter_int.h <= 0;  else  counter_int.h <= counter_int.h + 1;  end if;      -- Horizontal Sync Generation ('0')--  -- ------------------------------------__________-------  -- 0 659 755   if (counter_int.h <= 755) and (counter_int.h>= 659) then  VGA_HS <= '0';  else  VGA_HS <= '1';  end if;      -- 480 Horizontal Sync (pixel rows) Vertical Sync--   -- ---------------------------------------_______----------  -- 0 480 493-494 524  if (counter_int.v >= 524) and (counter_int.h >= 707) then  counter_int.v <= 0;  elsif counter_int.h = 707 then  counter_int.v <= counter_int.v + 1;  end if;    -- Vertical Sync Generation ('0') --  -- ---------------------------------------_______----------  -- 0 493-494   if (counter_int.v <= 494) and (counter_int.v >= 493) then  VGA_VS <= '0';  else  VGA_VS <= '1';  end if;      --Declares when blank will be low/active--  if counter_int.h<=639 then  VGA_BLANK_N<='1';  else   VGA_BLANK_N<='0';  end if;    --Declares when sync will be low/active--  if counter_int.v<=479 then  VGA_SYNC_N<='1';  else  VGA_SYNC_N<='0';  end if;    IF (counter_int.h < 640 AND KEY = "110") THEN  VGA_R <="11111111";    else  VGA_R <= "00000000";    end if;   IF (counter_int.h < 640 AND KEY = "101") THEN  VGA_B <="11111111";    else  VGA_B <= "00000000";    end if;   IF (counter_int.h < 640 AND KEY = "011") THEN  VGA_G <="11111111";    else  VGA_G <= "00000000";    end if;   end if;--if reset_n='0'  end if;--if rising_edge  end process process_sync_screen;   --End architecture--  end architecture vga; -----------------------------------------------------------------------------------------------------------------------------------------------------  What should i write in the testbench to make this work properly? Almost all of my signals are "undefinied". My stimuli is: KEY <= "111"; wait for 50 ns;   KEY <= "110";   wait for 50 ns; KEY <= "111"; wait for 50 ns; KEY <= "101";   wait for 50 ns; KEY <= "111"; wait for 50 ns;  KEY <= "011";   wait for 50 ns;   wait for 50 ns;  https://www.alteraforum.com/forum/attachment.php?attachmentid=8947   I would really be grateful if somebody helped with this.

[Altera_Forum]

Could you make the list with names a bit wider so we can see which signals are which?

[Altera_Forum]

https://www.alteraforum.com/forum/attachment.php?attachmentid=8948  

 Can you see wich signal is wich?

[Altera_Forum]

Am I correct in saying that VGA_CLK is never assigned a value? 

Check your errors and warnings. There you may find something that may help you find the problem.

[Altera_Forum]

--- Quote Start ---  Am I correct in saying that VGA_CLK is never assigned a value? Check your errors and warnings. There you may find something that may help you find the problem.  --- Quote End ---    Should I assign the value on the testbench? I can post the whole testbench and than maybe you can see were I went wrong. ----------------------------------------------------------------------------------------------------------------------------------------------  LIBRARY ieee;  USE ieee.std_logic_1164.all;   ENTITY test_vga_vhd_tst IS END test_vga_vhd_tst; ARCHITECTURE test_vga_arch OF test_vga_vhd_tst IS -- constants  -- signals  SIGNAL CLOCK_50 : STD_LOGIC := '0'; SIGNAL KEY : STD_LOGIC_VECTOR(2 DOWNTO 0); SIGNAL RESET_N : STD_LOGIC; SIGNAL VGA_B : STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL VGA_BLANK_N : STD_LOGIC; SIGNAL VGA_CLK : STD_LOGIC; SIGNAL VGA_G : STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL VGA_HS : STD_LOGIC; SIGNAL VGA_R : STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL VGA_SYNC_N : STD_LOGIC; SIGNAL VGA_VS : STD_LOGIC; COMPONENT test_vga  PORT (  CLOCK_50 : IN STD_LOGIC;  KEY : IN STD_LOGIC_VECTOR(2 DOWNTO 0);  RESET_N : IN STD_LOGIC;  VGA_B : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);  VGA_BLANK_N : OUT STD_LOGIC;  VGA_CLK : OUT STD_LOGIC;  VGA_G : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);  VGA_HS : OUT STD_LOGIC;  VGA_R : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);  VGA_SYNC_N : OUT STD_LOGIC;  VGA_VS : OUT STD_LOGIC  ); END COMPONENT; BEGIN  i1 : test_vga  PORT MAP ( -- list connections between master ports and signals  CLOCK_50 => CLOCK_50,  KEY => KEY,  RESET_N => RESET_N,  VGA_B => VGA_B,  VGA_BLANK_N => VGA_BLANK_N,  VGA_CLK => VGA_CLK,  VGA_G => VGA_G,  VGA_HS => VGA_HS,  VGA_R => VGA_R,  VGA_SYNC_N => VGA_SYNC_N,  VGA_VS => VGA_VS  );  CLOCK_50 <= not CLOCK_50 after 20 ns;  RESET_N <= '0', '1' after 50 ns;   init : PROCESS  -- variable declarations  BEGIN   -- code that executes only once   KEY <= "111";  wait for 50 ns;  KEY <= "110";  wait for 50 ns;  KEY <= "111";  wait for 50 ns;  KEY <= "101";  wait for 50 ns;  KEY <= "111";  wait for 50 ns;   KEY <= "011";  wait for 50 ns;   WAIT;  END PROCESS init;   always : PROCESS  -- optional sensitivity list  -- ( )  -- variable declarations  BEGIN   -- code executes for every event on sensitivity list  WAIT;  END PROCESS always;  END test_vga_arch;

[Altera_Forum]

The code works when I compile and then test it on the DE-2 board and I can change the colors on my computer screen.

[Altera_Forum]

A testbench is a piece of code that you can see as a testing environment. You take some signal generators, and current/voltage meters and probe every signal you like (!no variables). In order to do this you have to put some signals on the inputs of the level you want to test. For this you use a testbench. 

Try to look deeper in your design. How far do your signals carry? E.g. The 25 clock. Add this clock to the waveform and see if it works. If needs be you can do this for every signal by adding them in this way: "add wave top-level/lower_levels/signal_name".   Your simulation may have a problem in an incomplete sensitivity list, but I haven't checked this.

[Altera_Forum]

I'm still having trouble with my simulation. I'll try to talk with my instructor at the university.