Hi, How to choose the speed grade in an FPGA or CPLD?

[Altera_Forum]

Hi 

 I've a lot of questions about FPGAs and CPLDs speed grade, I want to generate a pulse of 3 ns acording to an event, which means that I need at least a 333 MHz clock, either external or using a PLL, right?   I don't understand the definition of speed grade, I found than means that an FPGA speed grade -10 for example, has a delay of 10 ns through macrocell, how this affect the maximum frequency supported? In the forum said that it depends of what I want to implement, I don't understand this either   Also, if I have an FPGA speed grade -6 (I read in a post that means 315 MHz) can I use an external clock of 300 MHz and try to obtain a higher frequency? the speed grade has to suport this new frequiency?  Speed grade definitions are equal in FPGAs and CPLDs?  If I don't need very much processing, only sample of events and generate pulses (3 ns), how can I decide which FPGA or CPLD buy?   Where can I find more information in order to undestand FPGAs an CPLDs work frequency?   I know that there are a lost of questions, I hope you can help me, thank you so much.

[Altera_Forum]

--- Quote Start ---   I want to generate a pulse of 3 ns according to an event   --- Quote End ---    What is the requirement for the timing relationship between the event and the pulse?  What is the logic level of the signal you are interfacing to, and what is the logic level of the pulse supposed to be?  The highest speed outputs on FPGAs are the LVDS and transceiver transmitter outputs. FPGA LVDS output signals can operate up to 800Mbps in the Cyclone devices, and the transceivers can operate at higher frequencies. Using these outputs, the speed grade becomes less of an issue.  Cheers, Dave

[Altera_Forum]

Hi, 

speed grade information in documentation is becoming border line useless, because modern devices are just so damn complicated. Synthesize your design (or a simplified version of it, if you don't have it yet) and see if it can meet the timing constrain. The simulation and synthesis tools can be downloaded for free from Altera's website, so you can do a lot of evaluation before commiting to a FPGA.  Note 1: using the DDR output cells, you maybe able to generate a 3 ns pulse using a 166 MHz clock. Note 2: The various speed grades of the same model are pin compatible, so you can leave the speed grade decision until you need to assemble the PCB. Note 3: It's just a bit more complicated, but a PCB can be designed to allow for different FPGA models (smaller or bigger), within the same FPGA family and package.

[Altera_Forum]

Thanks for answer XD  

 This is basically what I need, my input is a TTL signal: an aleatory pulse of 2.5 V amplitud and between 17 ns and 20 ns duration (the rising time is betwen 800 ps and 1 ns), I care for events, when I see one, I have to generate an output with a 3.3 ns duration, the amplitud its not realy important it may be 3.3 V or 2.5 V. I was thinking in sample this input with a 300 MHz clock, (external or generated from pll) because is the duration I need for my output, and its  enough for see the event.  But then I began to wonder about the speed grade, if the FPGA or CPLD can suport the frequency   I don't have experience with LVDS outputs so I will have to read about it before ask something, but It gives me the idea of working asynchronously, maybe this is not correct because I don't completely understand the concept of speed grade, but, if my FPGA is speed grade -5 (delay of 5 ns through macrocell) this means that If I see an event and generated an output signal, this signal have a delay of 5 ns without the need of a 200 MHz clock? I don't know if this make sense or I explain my idea, but thanks for reading it

[Altera_Forum]

--- Quote Start ---    using the DDR output cells, you maybe able to generate a 3 ns pulse using a 166 MHz clock  I didn't know that, I'm going to look more information about it, thanks : )

[Altera_Forum]

--- Quote Start ---   my input is a TTL signal: an aleatory pulse of 2.5 V amplitud and between 17 ns and 20 ns duration (the rising time is betwen 800 ps and 1 ns)   --- Quote End ---   Ok.    --- Quote Start ---   I care for events, when I see one, I have to generate an output with a 3.3 ns duration, the amplitud its not realy important it may be 3.3 V or 2.5 V.   --- Quote End ---   Why do you need to "see" another pulse? The FPGA could count the pulses if that is what you are interested in.    --- Quote Start ---   I was thinking in sample this input with a 300 MHz clock, (external or generated from pll) because is the duration I need for my output, and its  enough for see the event.   --- Quote End ---   No, its not.  Given that all you care about are events, you could use the pulse to toggle a signal internal to the FPGA. That toggle signal would stay at a logic high or low between events. Every time the toggle signal toggles is an 'event'. The clock frequency you need to detect events is then determined by the time *between* events, not the time of one pulse.  Read this article here and you will understand what I am talking about  http://www.edn.com/design/systems-design/4333702/crossing-the-abyss-asynchronous-signals-in-a-synchronous-world    --- Quote Start ---   It gives me the idea of working asynchronously   --- Quote End ---   If your pulses are not synchronous, then your system is already asynchronous.  Cheers, Dave

[Altera_Forum]

when you said "see" another pulse, you mean the output I want to generate?, and yes, I want to count, but in general what I want to to do is use an FPGA to replace a set of laboratory equipment that does the same thing (discriminator, logic unit), in order to compare, I have to generate the same output that the discriminator does  

 Thanks for the information, I'm going to read it, and I forgot to tell that the time between events is at least of 50 ns, and I have to study more about synchronous and asynchronous systems, because I believed that if my sampling method used or not a clock defined an synchronous or asynchronous system

[Altera_Forum]

Er... what do you mean by implementing a discriminator in the FPGA?

[Altera_Forum]

--- Quote Start ---  in general what I want to to do is use an FPGA to replace a set of laboratory equipment that does the same thing (discriminator, logic unit), in order to compare, I have to generate the same output that the discriminator does    --- Quote End ---   Before you create more work than you need, figure out what you really want. Just because your current lab system generates a pulse, it does not mean you need to duplicate that setup. You may be making things more complicated than needed.    --- Quote Start ---   Thanks for the information, I'm going to read it, and I forgot to tell that the time between events is at least of 50 ns, and I have to study more about synchronous and asynchronous systems, because I believed that if my sampling method used or not a clock defined an synchronous or asynchronous system  --- Quote End ---    Since the time between events is 50ns, the minimum toggle pulse high or low time is 50ns. You can easily synchronize that signal to a 100MHz clock (10ns period) and generate a synchronous pulse in the 100MHz clock domain. Those pulses can then be counted.  If what you really need is a count of events per second, you could easily create that using an FPGA. For example, every second your FPGA control logic can clear the event count, and start a 1s timer. During the 1s timer period your logic can count events using another counter. When the 1s counter is done, you will have a count of events for that second. You could display that on an LCD. The 1s counter would repeat every second, and the event counter would be cleared every second. The display would show the last 1s total event count.  With that in mind, think about what your current lab setup does, and what you really want. Chances are your FPGA can give you what you want without needing more test equipment.  Cheers, Dave

[Altera_Forum]

Thanks for the counting advices, that's just what I need, and you're right the final goal is to count the events 

 The current system has many stages because they can't just use the original signal to be an input for the counter, I know that I don't have to implement a discriminator in the FPGA, but in the end is my laboratory working for another laboratory, and to have this signal is one thing that they ask us to do, not sure if is only for see it or to be an input for another equipment or for comparison purposes, maybe they think that is necesary and that's why they want it  As far as I know they're interested in the count, there is a posibility of not implement this signal, after more meetings the details will be decided, but for now I have to consider that there is a chance, and I will have to do it, I wanted to be prepare and think in a way, thats why I began to wonder whats realy means speed degree

[Altera_Forum]

Keep in mind that whatever pulse you manage to generate will not be like any existing equipment. The "minimum" effort output pulse is to route the input signal directly back out to an output signal. However, there will be a minimum pulse width requirement. I have no idea what that is, because it would never be a good idea to do that in a 'real' design. If you wanted such a pulse, why not simply use an external comparator, or high-speed logic level translator? 

 You need to talk to your customers and ask what they really want. There's no point in you delivering something useless, and then having that reflect badly on you. You need to be up-front and tell them its a bad idea, or have them explain what it is they really want.  Cheers, Dave

[Altera_Forum]

I really appreciate the orientacion now I have more ideas, I prefer to keep it simple and don't do unnecessary things, I'm going to document myself and hope that if anything else comes up you can help me as always XD thanks