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Hierarchy not retained in Modelsim during RTL simulation

NShan12
New Contributor I
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Hello,

 

I am using QP 20.1.1 STD.

I have a hierarchical design (comprising VHDL and BDF flies), see screenshot (some names hidden):

NShan12_0-1645108492543.png

When I launch RTL Simulation from Quartus, I see that in Modelsim the same project hierarchy do not exist.

"proc_vhd_vec_tst" is my testbench and "i1" is the instance name of my VHDL top module in the testbench file.

As seen in the below screenshot, only ADC1_INST and ADC2_INST can be seen in the modelsim window and not the other instances such as PROC_1 and PROC_2.

NShan12_1-1645108688624.png

 

Therefore, I am not able to view the internal signals of sub modules in the wave window. How can I retain the hierarchy in modelsim to view the internal signals?

 

 

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SyafieqS
Moderator
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Naveen,


Seem like the other instance is not in Modelsim is due to unsupported format for Modelsim, you have to convert to HDl in order to simulate it.


https://www.intel.com/content/www/us/en/support/programmable/articles/000078436.html


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SyafieqS
Moderator
1,053 Views

Naveen,


Seem like the other instance is not in Modelsim is due to unsupported format for Modelsim, you have to convert to HDl in order to simulate it.


https://www.intel.com/content/www/us/en/support/programmable/articles/000078436.html


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