Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
Announcements
FPGA community forums and blogs on community.intel.com are migrating to the new Altera Community and are read-only. For urgent support needs during this transition, please visit the FPGA Design Resources page or contact an Altera Authorized Distributor.
21615 Discussions

High Performance DDR2 Controller

Altera_Forum
Honored Contributor II
1,242 Views

I'm developing a DDR2 High Performance Controller. When the megawizard was done, it said to make the <instance_name>_example_top_level.vhd as the top-level file. Do I only want to do that to test the DDR2 High perfromance controller? Is that test for simulation or for hardware tests? 

 

When my design is complete and I've added the rest of my logic, I only want to instantiate the <instance_name>.vhd correct, not the <instance_name>_example_top_level.vhd? 

 

Thanks!
0 Kudos
3 Replies
Altera_Forum
Honored Contributor II
564 Views

I use the ddr3 version and noticed the same thing. I just added the .QIP file to my project, and simply ignored the example_top stuff. I get a pile of warnings associated with not using it, but they seem harmless. I would be interested to hear any better ideas! 

 

Nick
0 Kudos
Altera_Forum
Honored Contributor II
564 Views

The "_example_top_level.vhd" file is just a top level example file for testing. 

 

Jake
0 Kudos
Altera_Forum
Honored Contributor II
564 Views

When I go instantiate my DDR2 controller component (as in add to the entire system), do I just instantiate my <instance_name>.vhdl or is there another file that I need to instantiate? 

 

Thanks
0 Kudos
Reply