High Speed Transceiver CDR Lock Time

[Altera_Forum]

I am investigate the possibility that using high speed SERDES of FPGA (such as Stratix IV or V GT) to cope with burst traffice in Passive Optical Network. 

In the Table 1. of Altera's Whitepaper WP-01143-1.2 "Implementing Next-Generation Passive Optical Network Designs with FPGAs", it says that CDR lock time is 267.64ns. But in Table 1-23 of Altera's Stratix IV Device Handbook's Chapter 1, the min value of Tltd_auto is 4000ns, which is higher than the value in whitepaper.  In my opionion, Tltd_auto is equal to CDR lock time, but there have difference between the whithpaper and handbook, which value is correct?  And How to measure the CDR lock time, can anyone give me reference documents related with burst cdr lock time measurement. Thank you in advance!

[Altera_Forum]

Hi HE_HAO, 

 Generally we should refer to the specs in the SIV device datasheet. As stated in datasheet, if your CDR is in Auto locking mode, then minimum CDR lock time to get valid data is 4000ns. However, if the CDR is in manual locking mode, which is you control the locking, the CDR lock time spec is max 4000ns. I believe the CDR lock time mentioned in the white paper is achieved using manual control of CDR lock mode. Note the in manual mode, the CDR lock time is calculate from rx_locktodata assertion to valid data recovered.