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Altera_Forum
Honored Contributor I
5,639 Views

High bandwidth data transfer between hps and fpga

Hi, 

I need to High bandwidth data transfer between hps and fpga. Which bridge should i use? I used light weight bridge but the speed of transfer data was up to 3MHz.  

Best Regards
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20 Replies
Altera_Forum
Honored Contributor I
351 Views

If you are using Cyclone V SoC, there are FPGA-to-HPS and HPS-to-FPGA bridge that lets you select AXI width of 32, 64 or 128-bits. These bridges can accommodate larger bandwidth compared to light weight bridge.

Altera_Forum
Honored Contributor I
351 Views

Many thak for your assistance . Is it possible to transfer data by using this bridge up to 100 MHz? how can i use this bridge ? Can you introduce me example code? 

Best Regards
Altera_Forum
Honored Contributor I
351 Views

In this example 

https://rocketboards.org/foswiki/view/projects/datamover 

 

it looks like the transfer from FPGA to HPS bridges are happening at 133MHz (multiply that with 128-bit, so 2.1GB/s assuming that the pipeline can be saturated) 

 

It you just wanted to access the HPS SDRAM and do not need coherency, you can use the FPGA-to-SDRAM bridge instead - here's an example implementation: 

https://rocketboards.org/foswiki/view/projects/cyclevsocsdramperformanceexampledesign 

 

Hope this helps...
Altera_Forum
Honored Contributor I
351 Views

Many thanks for your assistance. I am beginner to HPS. can you introduce me an easy example? I can not understand the role of onchip_memory and another Qsys blocks. is it better for me to start this project step by step.

Altera_Forum
Honored Contributor I
351 Views

Hi, 

i used h2f_axi_master by address 0xc000000 in the linux. I this state the rate of transformating was low. What is the reason?should i use bare instead of linux?
Altera_Forum
Honored Contributor I
351 Views

The On Chip memory in the FPGA is just a Avalon Memory component - in theory, you can replace this with another component (including your own custom component) 

 

I'm not sure if the OS is hindering the transfer rate (could be due to various other reasons as well) - as you can see from the example above, you may want to consider using DMA in the FPGA to help speed things up. If you are letting the processor to do all the copying of the data, it may slow things down due to overheads, etc. 

 

Are you performing the transfer from HPS --> (your custom Qsys component)?
Altera_Forum
Honored Contributor I
351 Views

Hi, 

I transfer from HPS to FPGA IO pins. 

Mang thanks for your assistance
Altera_Forum
Honored Contributor I
351 Views

Since you are connecting it to the FPGA IO, I assume that you've created a "PIO" Qsys component and connect the HPS-FPGA bridges to it. The HPS-FPGA bridge is not really efficient for such scenarios (it works better when connected to a FPGA master that requires wide data width). Perhaps it would be better to see if the FPGA IO can be controlled using IP within the FPGA, and use the HPS-FPGA lightweight bridge to update/change the registers for the FPGA IP.

Altera_Forum
Honored Contributor I
351 Views

Hi, 

I do not understand your opinion? can you explain it with an example? I am trying to do it without IP. 

many thanks
Altera_Forum
Honored Contributor I
351 Views

There is a design that I saw somewhere (not the Datamover) that better demonstrate the usage of the bridge. I'll try to find and post it here.

Altera_Forum
Honored Contributor I
351 Views

Here is the design that I was referring to: 

https://www.altera.com/support/support-resources/design-examples/soc/fpga-to-hps-bridges-design-exam... 

 

There are examples for both Cyclone V and Arria 10. It focuses on the high bandwidth F2H and F2S bridges. Hope this will help
Altera_Forum
Honored Contributor I
351 Views

Ok . Many thanks. I will walk through this example and will send feedback on it.

Altera_Forum
Honored Contributor I
351 Views

 

--- Quote Start ---  

Here is the design that I was referring to: 

https://www.altera.com/support/support-resources/design-examples/soc/fpga-to-hps-bridges-design-exam... 

 

There are examples for both Cyclone V and Arria 10. It focuses on the high bandwidth F2H and F2S bridges. Hope this will help 

--- Quote End ---  

 

 

Hi sunshine, 

Thanks for the reference link, but I can't compile the fpga project to make the output file .sof compatible with my kit. Beside, the hps_system.qsys is missing 3 subcomponents: AXI_cache_security and custom_reset_synchronizer_50, custom_reset_synchronizer_fast. 

Could you give me some advice to make it work? I'm expecting to transfer data between FPGA and linux application with bandwidth >= 60MB/s ~ 480Mb/s and I wonder whether this example can reach this requirement 

I'm using DE1-SOC kit and Quartus 15.0.
Altera_Forum
Honored Contributor I
351 Views

 

--- Quote Start ---  

Hi sunshine, 

Thanks for the reference link, but I can't compile the fpga project to make the output file .sof compatible with my kit. Beside, the hps_system.qsys is missing 3 subcomponents: AXI_cache_security and custom_reset_synchronizer_50, custom_reset_synchronizer_fast. 

Could you give me some advice to make it work? I'm expecting to transfer data between FPGA and linux application with bandwidth >= 60MB/s ~ 480Mb/s and I wonder whether this example can reach this requirement 

I'm using DE1-SOC kit and Quartus 15.0. 

--- Quote End ---  

 

 

You'll need to Open Qsys and generate the HDL files first. After that, then you can compile the design
Altera_Forum
Honored Contributor I
351 Views

As a general rule of thumb the highest speed method of moving data between the FPGA and HPS is to use the FPGA-to-SDRAM interface. If you require the FPGA to have access to cacheable data then that's the exception to the rule and you would use the F2H bridge (and a master in the FPGA) instead. I would stay away from moving data between the FPGA and HPS using the MPU or DMA inside the HPS which is why that design sunshine pointed to doesn't bother to implement it.

Altera_Forum
Honored Contributor I
351 Views

 

--- Quote Start ---  

As a general rule of thumb the highest speed method of moving data between the FPGA and HPS is to use the FPGA-to-SDRAM interface. If you require the FPGA to have access to cacheable data then that's the exception to the rule and you would use the F2H bridge (and a master in the FPGA) instead. I would stay away from moving data between the FPGA and HPS using the MPU or DMA inside the HPS which is why that design sunshine pointed to doesn't bother to implement it. 

--- Quote End ---  

 

I have followed the example which sunshine recommended and make my system works as: 

1. Load my data in FPGA layer to a FIFO 

2. Using msgDMA to transfer data from the fifo to a sdram port, lightweight h2f bridge is used to control msgdma only. 

3. In my linux application, I read the data from sdram using mmap and it worked well. 

However, there is some troubles 

1. The read data from sdram will be processed with some heavy works such as applying filter, image processing, and using TCP/IP to transfer the processed data to other host PC. All the heavy works make my kit slow down and effect to the sampling frequency of my data in fpga.  

Therefore, I'm thinking of transferring my data directly from the sdram to ethernet using the HPS EMAC controller and my question is how do I configure some parameters of TCPIP socket as the host IP address, port, etc. I'm expecting to achieve highest bandwidth as high as possible. 

2. My flow is too complicated now,  

data(fpga) --> fifo --> dma --> sdram --> dma --> ethernet emac --> TCPIP--> host PC. 

but it's the easiest flow I can merge from multiple examples on the internet. Could you give me some advice to simple the flow?
Altera_Forum
Honored Contributor I
351 Views

 

--- Quote Start ---  

I have followed the example which sunshine recommended and make my system works as: 

1. Load my data in FPGA layer to a FIFO 

2. Using msgDMA to transfer data from the fifo to a sdram port, lightweight h2f bridge is used to control msgdma only. 

3. In my linux application, I read the data from sdram using mmap and it worked well. 

However, there is some troubles 

1. The read data from sdram will be processed with some heavy works such as applying filter, image processing, and using TCP/IP to transfer the processed data to other host PC. All the heavy works make my kit slow down and effect to the sampling frequency of my data in fpga.  

Therefore, I'm thinking of transferring my data directly from the sdram to ethernet using the HPS EMAC controller and my question is how do I configure some parameters of TCPIP socket as the host IP address, port, etc. I'm expecting to achieve highest bandwidth as high as possible. 

2. My flow is too complicated now,  

data(fpga) --> fifo --> dma --> sdram --> dma --> ethernet emac --> TCPIP--> host PC. 

but it's the easiest flow I can merge from multiple examples on the internet. Could you give me some advice to simple the flow? 

--- Quote End ---  

 

 

Hello, 

 

we have implemented "High-Bandwidth" data transfer using the sdram to Ethernet-method with Cyclone V SoC. The data flow is data(fpga)->sdram->HPS EMAC -> TCP/IP -> Host PC. We get about 200 Mbit/s throughput with this method. The bottleneck of this method is the Sdram-controller's maximum clock speed which is 300-367 MHz (dependig on the device's speed grade). So this method would maybe not work for you if want to get at least 480 Mbit/s throughput.
Altera_Forum
Honored Contributor I
351 Views

 

--- Quote Start ---  

Hello, 

 

we have implemented "High-Bandwidth" data transfer using the sdram to Ethernet-method with Cyclone V SoC. The data flow is data(fpga)->sdram->HPS EMAC -> TCP/IP -> Host PC. We get about 200 Mbit/s throughput with this method. The bottleneck of this method is the Sdram-controller's maximum clock speed which is 300-367 MHz (dependig on the device's speed grade). So this method would maybe not work for you if want to get at least 480 Mbit/s throughput. 

--- Quote End ---  

 

 

Thanks for reminding. It seems like my flow currently, but I wanna give it a try. :confused: 

How do you configure the flow from sdram to TCP/IP? Where can I configure the IP address, port for socket? Could you share some ideas to implement it?
Altera_Forum
Honored Contributor I
351 Views

 

--- Quote Start ---  

Thanks for reminding. It seems like my flow currently, but I wanna give it a try. :confused: 

How do you configure the flow from sdram to TCP/IP? Where can I configure the IP address, port for socket? Could you share some ideas to implement it? 

--- Quote End ---  

 

 

I'm not a software guy, so I cannot give any detailed advice on this. But I guess you are using Linux in your system. The ethernet settings can be configured using /etc/network/interfaces.
Altera_Forum
Honored Contributor I
130 Views

 

--- Quote Start ---  

I'm not a software guy, so I cannot give any detailed advice on this. But I guess you are using Linux in your system. The ethernet settings can be configured using /etc/network/interfaces. 

--- Quote End ---  

 

 

yeah, I'm running Linux system, but I'm thinking about other way. 

I read the technical reference of Cyclone V there is a DMA controller in EMAC module so I wanna use this DMA (or an external mgsDMA is ok) to forward my data from SDRAM directly to EMAC which support Reduced Gigabit Media Independent Interface (RGMII). 

If I load the data from sdram to Linux application and use Linux socket to forward to the host PC, I think this way can't give a better solution than the above.
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