High speed Clock generation by ALTPLL Cyclone III

[Altera_Forum]

hello, 

 i have a problem to use the high speed clock generated by ALTPLL. I have the Cyclone III EP3C25F324 FPGA starter board. There is an 50MHz on-board oscillator for PLL. I need a high speed clock of 1200MHz. It is only for intern logic operation, output pins have a maximal frequency of 5 MHz. According to data sheet it is possible to get a clock up to 1300MHz using ALTPLL (Clock multiplication faktor and division faktor).    Below are my experments: Multiplication faktor = 8 and divison faktor = 1 --> output clock = 400MHz, started compliation, ok.   Multiplication faktor = 16 and divison faktor = 1 --> output clock = 800MHz, started compilation, occoured this warning: "Critical Warning: ... wire_pll1_clk[0] feeding the core has illegal output frequency of 800 MHz that must be less than 472.6 MHz" However, the compilation was succesful. my question, can i use it ???   tanks a lot.   ruan

[Altera_Forum]

I'm willing to believe the hardware manual, that a clock frequency above 500 MHz can't be distributed by the Cyclone III clock network. Furthermore, you won't be able to operate logic at 800 or even 1200 MHz because the propagation delays don't allow feedback without timing violations. 

 Faster FPGA families (e.g. Stratix IV) achieve up to 800 MHz core clock frequency. Direct 1200 MHz logic operation isn't an option even with the fastest FPGA. But multi-bit parallel processing and double data rate I/O interfaces may be able to achieve the intended logic operation speed anyway.

[Altera_Forum]

thank you for your answer. 

 I simulated the logic function with the timing simulation tools, it's all correct with clock of 800MHz, above this frequency was then false. I don't understand why did the MegWizard Plug-In Manager (configuration of PLL output clock) allow to set to the clock up to 1300MHz, if this clock can not be distributed by Cyclone III? Is it a bug of Altera?