I am using Cyclone 10LP in my design and I want to use PLL3 instead of PLL1, by default the compiler selects the PLL1.
This is an existing design which uses FPGA cyclone III and the software version is 13. There is only one PLL which is PLL3. The physical connections on the PCB are for PLL3 output. I have updated the FPGA to cyclone 10LP and have updated the PCB with new FPGA, could not asses this side, now the PCB is manufactured and I am not getting any output clock from PLL3.
I have looked into the documentation of ALTPLL but could not find anything. Can you please help me in this?
Really apology for been in late reply, some internal tool issue was there to assign your case to me.
From your question , what I understood is when you change the pll in Quartus design for Cyclone 10 LP , quaruts is giving the compilation Error . And the PCB is already manufactured by assuming a different PLL.
if the case is above , may I request to instantiate clock control block and assign the clock to global and can you give to PLL .