In my design there's a 5G 4X Rapid IO IP Core. A single TX PLL is instantiated to drive
I've tried to drive the sysclk signal with txclk(output from the RapidIO IP Core) and a
250MHz clock(output from a IO_PLL IP Core), both of the two cases got negative setup slacks
after timing analysis, which result in error data in rapidio packet, as you can see in the
The frequency of reference clock is 100MHz.
Yes, please send your design to my email address firstname.lastname@example.org
Anyway from your latest description, I am able to identify some incorrect clock connection information. syslck is the avalon sysclk. Connecting to tx_clk (which is sourced from transceiver PLL) is not recommended. Hence, please connect to IO PLL IP core. Also ensure the recommended frequency for sysclk is met. Currently you seem to be suing 250MHz which does not meet the maximum recommended frequency .Its documented in Table 16 of the RapidIO User Guide below:
Please update your clock connections following the user guide.