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How can I eliminate negative slack in RapidIO IP Core

SYiwe
Novice
810 Views

Hi,

 

In my design there's a 5G 4X Rapid IO IP Core. A single TX PLL is instantiated to drive 

 

tx_bonding_clock_ch0~3.

 

I've tried to drive the sysclk signal with txclk(output from the RapidIO IP Core) and a 

 

250MHz clock(output from a IO_PLL IP Core), both of the two cases got negative setup slacks 

 

after timing analysis, which result in error data in rapidio packet, as you can see in the 

 

following screenshot.

negative slack in rapidio ip core.PNG

The frequency of reference clock is 100MHz.

Any suggestions? 

 

Thanks, regards.

 

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Nathan_R_Intel
Employee
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Hie, From your description alone, I cannot determine what is causing the timing error. Could you attach your design achieve (.qar), together with which Quartus version used for me to help you with this error. Regards, Nathan
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SYiwe
Novice
534 Views

Thanks.

Can you give me an email address so I can send my design to you?

Regards.

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Nathan_R_Intel
Employee
534 Views

Hie,

 

Yes, please send your design to my email address nathan.ramachandran@intel.com

 

Anyway from your latest description, I am able to identify some incorrect clock connection information. syslck is the avalon sysclk. Connecting to tx_clk (which is sourced from transceiver PLL) is not recommended. Hence, please connect to IO PLL IP core. Also ensure the recommended frequency for sysclk is met. Currently you seem to be suing 250MHz which does not meet the maximum recommended frequency .Its documented in Table 16 of the RapidIO User Guide below:

 

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_rapidio.pdf

 

Please update your clock connections following the user guide.

 

Regards,

Nathan

 

 

 

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