Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
20824 Discussions

Triple speed example design for Cyclone V GT dev kit

JMedi
Beginner
530 Views

The board update portal example ​project use ETH but use old Quartus version and It can't build meeting timing constraint.

0 Kudos
1 Reply
Deshi_Intel
Moderator
287 Views
0 Kudos
Reply