I am developing 10G application on FPGA and I am facing with next problem:
I have plenty of timing errors in 10GBASER phy core on clok nets xv_xcvr_10gbaser_nr_inst|ch[*].sv_xcvr_10gbaser_native_inst|native_inst|inst_sv_pma|rx_pma.sv_rx_pma_inst|rx_pmas[*].rx_pma.rx_pma_deser|clk90b
I am using Quartus 18.1 under windows.
Before, I am using this core in other designs and never faced with such type of problem. May be one difference with that before - here I am try to use 4 channels on Tile instead one.
I always think that the 10G core is the hardcore and its timing constraints are meet automatically.
I try different settings of the fitter and synthesis but they not bring results.
Can someone advise how to proceed to overcome this problem.
It is begin to be very critical.
Thank you in advance.
Nevermind, already solve it after write this post.
Problem was in some not working guard variables in sdc files where derive clock was not done, but in timequest was.