Did anybody have any experience with setting up the DFE (Decision Feedback Equalization) for the 10G transceivers inside the Cyclone 10GX?
The easy way to set the analog parameters for signal equalization (in the Rx direction) is to use the Transceiver Toolkit (TTK) feature – see “Quartus/Tools/System Debugging Tools/Transceiver Toolkit”. Ideally, we would like to set the taps for the DFE using the PHY IP gen or the Assignment Editor or some registers that we can access via the Avalon-MM interface.
The DFE has 3 modes: OFF, Manual and Adaptation Enabled. It is this last setting (Adaptation Enabled) that we would like to set (as we do using the TTK), but there is no Cyclone 10GX doc to explain that. The register map for the Cyclone 10GX (see attached Excel) points us to Chapter 5 of the Arria 10 PHY doc (also attached), which in turn points to a specific tab (DFE Adaptation Tool) in the other attached Excel file for the Arria 10 register map.
So far, I found two descriptions for turning ON the Adaptive DFE mode, one for Stratix V and one for Arria 10; I assume the latter can be applied to our Cyclone 10 GX. Can somebody please confirm that we can use the procedure described on pages 465-466 of the attached Arria PHY doc? The registers required for the Cyclone 10GX DFE setup should be different from the ones mentioned in the Arria 10 doc.
Also, can somebody confirm what happens with the DFE taps after they are set by the internal adaptive engine? From what I read in Table 122 of the attached Arria 10 PHY doc (page 155), if bit 19 at address 0x4D0 is set to 0, then bits 20 and 21 decide what happens with these DFE taps. What is the default value for bit 19? What exactly is the meaning of “a default value for hardware” and “a default value for simulation”? - see the row for bit 19 on page 155. From what I see when I use the TTK, these taps are frozen once they are set, until another “Adaptation” is triggered manually from one of the TTK radio buttons, or until another power-up happens.
Last question: from the 11 DFE taps, I assume Cyclone 10 GX has only 2 fixed taps (4 and 8) that should be set in Manual mode. Am I right? Are the other taps used in the Adaptive mode together with the fixed ones? Are the two fixed ones (4 and 8) enough for the DFE process if we were to use the Manual mode, instead of the Adaptive mode?
Once again, we do not want to use the Manual mode to set these DFE taps via the Assignment Editor. We would rather use the AVMM interface to Enable the Adaptive mode, so I assume the top part of page 465 should be what we would implement for this procedure.
All registers and bits mentioned above should change for Cyclone 10GX, but all that I have now (as an example) for setting up the DFE relates to Arria 10.
Many thanks in advance.
I verified using Quartus v18.0. Looks like Quartus v18.0 NativePHY IP IP doesn't support DFE setting as well. Only CTLE setting is shown in attached screenshot pic.
In short, the only escapee loophole is on ttk and Quartus assignment editor setting while NativePHY IP had mask off DFE setting. Cyclone 10 GX user guide also never mentioned about DFE support.
I have checked internally within Intel.
I apologize for the confusion caused on ttk and Quartus assignment editor setting
BUT my advice to you is to not use DFE on Cyclone 10 GX as I can't guarantee whether it will work or not. I also don't have DFE register address mapping table to share with you as it's not supported feature yet.
Your understanding is highly appreciated here.