How can I set the DFE (Decision Feedback Equalization) in Adaptive Mode for the 10G transceivers inside Cyclone 10 GX?

BAnto3 · ‎07-02-2019

Hi All,

Did anybody have any experience with setting up the DFE (Decision Feedback Equalization) for the 10G transceivers inside the Cyclone 10GX?

The easy way to set the analog parameters for signal equalization (in the Rx direction) is to use the Transceiver Toolkit (TTK) feature – see “Quartus/Tools/System Debugging Tools/Transceiver Toolkit”. Ideally, we would like to set the taps for the DFE using the PHY IP gen or the Assignment Editor or some registers that we can access via the Avalon-MM interface.

The DFE has 3 modes: OFF, Manual and Adaptation Enabled. It is this last setting (Adaptation Enabled) that we would like to set (as we do using the TTK), but there is no Cyclone 10GX doc to explain that. The register map for the Cyclone 10GX (see attached Excel) points us to Chapter 5 of the Arria 10 PHY doc (also attached), which in turn points to a specific tab (DFE Adaptation Tool) in the other attached Excel file for the Arria 10 register map.

So far, I found two descriptions for turning ON the Adaptive DFE mode, one for Stratix V and one for Arria 10; I assume the latter can be applied to our Cyclone 10 GX. Can somebody please confirm that we can use the procedure described on pages 465-466 of the attached Arria PHY doc? The registers required for the Cyclone 10GX DFE setup should be different from the ones mentioned in the Arria 10 doc.

Also, can somebody confirm what happens with the DFE taps after they are set by the internal adaptive engine? From what I read in Table 122 of the attached Arria 10 PHY doc (page 155), if bit 19 at address 0x4D0 is set to 0, then bits 20 and 21 decide what happens with these DFE taps. What is the default value for bit 19? What exactly is the meaning of “a default value for hardware” and “a default value for simulation”? - see the row for bit 19 on page 155. From what I see when I use the TTK, these taps are frozen once they are set, until another “Adaptation” is triggered manually from one of the TTK radio buttons, or until another power-up happens.

Last question: from the 11 DFE taps, I assume Cyclone 10 GX has only 2 fixed taps (4 and 8) that should be set in Manual mode. Am I right? Are the other taps used in the Adaptive mode together with the fixed ones? Are the two fixed ones (4 and 8) enough for the DFE process if we were to use the Manual mode, instead of the Adaptive mode?

Once again, we do not want to use the Manual mode to set these DFE taps via the Assignment Editor. We would rather use the AVMM interface to Enable the Adaptive mode, so I assume the top part of page 465 should be what we would implement for this procedure.

All registers and bits mentioned above should change for Cyclone 10GX, but all that I have now (as an example) for setting up the DFE relates to Arria 10.

Many thanks in advance.

Bogdan

Deshi_Intel · ‎07-03-2019

HI, Can you confirm again are you using Cyclone 10 GX or Arria 10 FPGA ? The reason I asked is due to Cyclone 10 GX doesn't support DFE, only CTLE and VGA. You can check it out via Cyclone 10 GX NativePHY IP or below user guide link https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyclone-10/ug_cyclone10_xcvr_phy.pdf There is no mention of DFE in Cyclone 10 GX. DFE is only supported in Arria 10 FPGA. Thanks. Regards, Deshi

BAnto3 · ‎07-03-2019

Hi Deshi, Thanks so much for the quick reply … yes, we are using the Cyclone 10GX … NOT the Arria 10 … but, I had no documentation for the DFE feature, so I tried to read anything that I found on-line, thinking that I can apply it somehow to our Cyclone 10GX. I am surprised by your answer, though. The Cyclone 10 GX supports DFE … I am able to set it using the TTK in Quartus (see my previous message) … all 3 modes: OFF, Manual or Adaptive … we are also able to set various taps using the Assignment Editor or even using the PHY IP gen … the problem with these two last options is that we have to set specific values for specific taps … I want to set ONLY the Adaptive mode, so I do not bother with these tap values … as I said, I can do that now with the TTK … BUT, this is not something that I can do for a series production. So, once again why do you say that DFE is not available for Cyclone 10 GX? Looking forward to hearing from you. Bogdan

Deshi_Intel · ‎07-04-2019

Hi Bogdan, Now I am confused as well due to discrepancy of info around. :) I suspect this is due to earlier version of Quartus bug that they forgot to disable the DFE setting but then Quartus disable DFE and fix it in later Quartus version. In latest Quartus version like v19.1 pro edition, NativePHY IP no longer show DFE setting and you also can't find the DFE register mapping in c10-registermap.xlsx May I know which Quartus version that you are using ? I will also try to check internally within Intel FPGA to clarify on the DFE support plan for Cyclone 10. Thanks. Regards, dlim

BAnto3 · ‎07-05-2019

Hi Deshi, That explains why we see different things ☺ … indeed, my version is 18.0 pro edition build 219 … or at least the one that I have in the lab on the laptop used for TTK experiments. Yes, it would be good to find out what DFE support plans Intel has. Also, if the TTK, the PHY IP gen and the Assignment Editor in our version set some values for the DFE taps, can we really count that these taps are really set? In other words, can you please provide the Cyclone 10 GX register map prior to removing the DFE registers in your rev 19.1? These DFE values must go somewhere. So, we need to know those registers, in order to turn ON that DFE Adaptive mode using the register set (i.e., implement the procedure described for Arria 10, but using the Cyclone 10GX DFE registers). Many thanks, once again. Bogdan

Deshi_Intel · ‎07-09-2019

HI Bogdan,

I verified using Quartus v18.0. Looks like Quartus v18.0 NativePHY IP IP doesn't support DFE setting as well. Only CTLE setting is shown in attached screenshot pic.

In short, the only escapee loophole is on ttk and Quartus assignment editor setting while NativePHY IP had mask off DFE setting. Cyclone 10 GX user guide also never mentioned about DFE support.

I have checked internally within Intel.

Basically Cyclone 10 GX DFE is a hidden feature reserved for future use but as of now there is NO official support plan from Intel
I am sorry but my answer to your question - "can we really count that these taps are really set?" is I am not sure as it's not tested feature in Cyclone 10 GX.
Intel marketing decided to remove the support for DFE feature due to it's consuming more power and it's not meant to be used for lower end FPGA like Cyclone 10 GX. DFE is supported for mid range FPGA like Arria 10 and also on high end FPGA like Stratix 10.

I apologize for the confusion caused on ttk and Quartus assignment editor setting

BUT my advice to you is to not use DFE on Cyclone 10 GX as I can't guarantee whether it will work or not. I also don't have DFE register address mapping table to share with you as it's not supported feature yet.

Your understanding is highly appreciated here.

Thanks.

Regards,

dlim

BAnto3 · ‎07-09-2019

Deshi_Intel · ‎07-10-2019

Hi Bogdan, Really appreciate your understanding on the DFE support plan for Cyclone 10 GX. Now, let me check out the support plan for EyeQ on Cyclone 10 GX as well. I am not optimistic when you mentioned EyeQ feature selection is grey out in ttk. Nevertheless, let me find out first before I get back to you. Thanks. Regards, dlim

Deshi_Intel · ‎07-12-2019

HI Bodgan, I found below link that clearly clarify the supported feature on transceiver toolkit. https://www.intel.com/content/www/us/en/programmable/products/design-software/fpga-design/quartus-prime/features/swf-transceiver-toolkit.html Refer to table 1. It shown eye viewer feature is not supported on both Cyclone 10 and Arria 10 FPGA and only supported on Stratix 10. Thanks. Regards, dlim