How can I translated VHDL to Verilog HDL.

Altera_Forum · ‎08-02-2009

The problem is how can I deal with the posedge and negedge with the same signal.

 
process(Timer) 
begin
if Timer'event and Timer='1' then --Timer rising edge.
trise<='1';
start = 1;
elsif Timer'event and Timer='0' then --Timer falling edge.
trise<='0';
hold = 1;
end if;
end process;

Altera_Forum · ‎08-03-2009

Try this:

always @(Timer)

begin

if (Timer)

begin

trise = 1;

start = 1;

end

else

begin

trise = 0;

hold = 1;

end

Of course, this is not synthesizable but should work in simulation.

Regards,

Harald

Altera_Forum · ‎08-07-2009

--- Quote Start ---

Try this:

always @(Timer)

begin

if (Timer)

begin

trise = 1;

start = 1;

end

else

begin

trise = 0;

hold = 1;

end

Of course, this is not synthesizable but should work in simulation.

Regards,

Harald

--- Quote End ---

Thanx, Harald, it seems better than what I think! :)