How could I understand “IOPLL could drive the lvds tx transmitter in adjacent bank"

[lambert_yu]

Hi,

   In the "arria 10 Core Fabric and General purpose I/O handbook ":

   There 's one sentence "For differential transmitters, the PLL can drive the differential transmitter channels in its own I/O bank and adjacent I/O banks". And I followed this to build one design as below:

    1. refclk : refclk_0p from 2F bank

    2. IOPLL :  use internal pll in lvds IP configuration

    3.  tx transmitter: one channle in 2F bank, 4 channel in 2G bank (they are all not continous)

    4. output the txclk_out

   When I compiled the design, there's fitter error  Error(14566), Error (175006).

   I don't know where's error? Will I need to modify some part to complete this design?

   maybe :

   Solution 1: modify item2, use the external PLL?

   Solution 2 : only use the IOPLL, refclk, lvds tx transmitter in the same bank.

   Could someone help me about this?

Best Regards,

Lambert

[FvM]

Hi,
error message is incomplete, fitter also reports which signal can't be routed along with Error (175006).

Simple solution would be: Use separate IOPLL in 2F and 2G TX serdes, reference clock can be routed from other bank for TX PLL (but not for RX PLL).

Using the same IOPLL for multiple (adjacent banks) requires implementaion as external PLL, I think. Otherwise no PLL clock is available for routing. This saves an IOPLL resource but requires more clock wiring and involves the possible risk to define an incorrect PLL configuration. Quartus however reports the required external PLL settings when implementing SERDES.

[lambert_yu]

Hi, FvM

    I presented the detail error message:

    (you maybe need to zoom in this page and could see the content clearly) ( because there's image upload policy, I could not provide the original picture)

    Simple solution would be: Use separate IOPLL in 2F and 2G TX serdes, reference clock can be routed from other bank for TX PLL (but not for RX PLL).

     For this case, I only used the lvds channels in bank 2G, but there's refclk issue and it's not easy to provide other clock source to its refclk pin due to the board design. And it's easy to provide one external clock to the refclk pin of bank 2f.

    And I have tried to use the external IOPLL (refclk comes from BANK 2F),  I added 1 dummy lvds transmitter in bank 2f which is not the real used and 4  lvds transmitter in bank 2g which are real used. But there's still fitter error.

   My fpga is : 10ax115n2f45e1sg

Best Regards,

Lambert

[FvM]

Hi,
I tried to trace the problem in Quartus Pro, versions 22.4 and 25.1.

According to my reading of
Intel® Arria® 10 Core Fabric and General Purpose I/Os Handbook 2023.01.18, it should be possible to drive SERDES TX IOPLLs in multiple banks from a single refclk pin.
"5.6.6.2.2. Guideline: I/O PLL Reference Clock Source for DPA or Non-DPA Receiver

The reference clock to the I/O PLL for the DPA or non-DPA LVDS receiver must come from the dedicated reference clock pin within the I/O bank.

Note: This requirement is not applicable to LVDS transmitters."

But apparently this doesn't work. Without global_clock assignment for the refclk pin, you get routing error described in above posts. With global_clock assignment (which seems appropriate to me), the error turns into well-known Error(18694) "): The reference clock on PLL (...) is not driven by a dedicated reference clock pin from the same bank."

But according to above quoted note, the requirement doesn't apply to SERDES TX PLL.

I'm under the impression that Quartus fitter constraints are not accordance with A10-Handbook specifications and that the requested SERDES TX configuration can't be implemented without using undocumented Quartus settings.

Regarding other option, using a single PLL for adjacent SERDES TX banks, it's not completely clear what "only" in Pragraph 5.6.6.5. Guideline: Pin Placement for Differential Channels means.

"The I/O bank PLL can drive the differential transmitter channels in an adjacent I/O
bank only in a wide LVDS SERDES Intel FPGA IP transmitter interface that spans multiple I/O banks, where:
• With tx_outclock enabled—the transmitter has more than 22 channels
• With tx_outclock disabled—the transmitter has more than 23 channels"

I understand "wide SERDES" as single instance driving pins in multiple adjacent banks. But is it required to use all 22 pins in a bank to advance to next bank? If not, why is the pin count mentioned at all?

[FvM]

Hi,
"wide LVDS SERDES" option seems to solve the problem. Define a single TX SERDES instance with outputs in multiple adjacent banks. IOPLL is generated in the refclk pin bank, LVDS clock tree is propagated to adjacent banks where needed.

[lambert_yu]

hi,

  Define a single TX SERDES instance with outputs in multiple adjacent banks. IOPLL is generated in the refclk pin bank, LVDS clock tree is propagated to adjacent banks where needed.

    For this, I could get your point and I had did this design.

 "wide LVDS SERDES" option seems to solve the problem 

    For this senstence, I could not understand. You means that I need set  multi-channel which are located in adjacent banks in one TX SERDES IP ?  ( I had tried this).

[FvM]

Hi,

please check example design, it uses Bank 2F refclk and TX pins in Bank 2F and 2G.

[lambert_yu]

Hi, FvM

    Thanks for your strong support.

    By the way,  I will need  version 22.4 and 25.1 to open it? But I am not have them, would you please to help to  provide one under version 19.1?

Best Regards,

Lambert

[FvM]

Are you using Quartus 19.1 Std. for Arria 10? Didn't expect, never used Arria 10 with Quartus Std. I need to regenerate SERDES IP.

[lambert_yu]

We used Quartus Prime Version 19.1.0.

[FvM]

Hi,

test with Quartus V19.1.0 Std. 

[lambert_yu]

Thanks for your strong support again!

 I thought I found the different point with your design, you didn't select Enable tx_outclock port under Transmitter Setting. When I set this option in your design,  I met the same issue which likes the previous issue.

  I want to know the reason for this option, because there's no instructions in guide.

  Could  you help me?

[FvM]

Hi,
can't confirm this problem, bank spanning large SERDES works for me with clock output as well. Check appended test design.

General, clock output can be used to clock the receiver if it isn't able to extract clock from data stream, or the protocol isn't prepared for this option, e.g. not using 8b10b coding with dedicated sync characters.

Related to SERDES IP, clock output isn't but another TX channel sending a fixed pattern.

Regards
Frank

[lambert_yu]

Oh, it's weird.

My quartus is Quartus Prime Version 19.1.0 Build 240 03/26/2019 SJ Pro Edition.

 May be there's any Patches which I need to install?

[FvM]

HI, you previously wrote "Quartus Prime Version 19.1.0.", as we hear now it's Quartus Prime Pro 19.1.0. Unfortunately I don't have older Pro version than 22.4 installed.

[FvM]

Hi,
I found that above posted .qar file generated with Quartus V19.1 Std. can be flawlessly imported in Quartus Pro, your V19.1.0 or any newer version. All you need to do is to regenerate SERDES IP.

[lambert_yu]

Yes, I just updated the IP and select the enable tx_outclock port.

[FvM]

With which result? SERDES TX driven by PLL in adjacent banks works for me with all tested Quartus versions, Std. and Pro. But as stated, you need to use the "wide SERDES" approach, using only a single SERDES TX instance that drives all TX pins. They can be either located in the PLL bank, defined by refclk pin location or both adjacent banks.

[lambert_yu]

I found affecting factor : Desired tx_outclock phase shift(degress) under Transmitter Settings 

 When I set it to non-zero value, fitter will report the error which likes the previous.

[FvM · Accepted solution]

Hi,

that sounds plausible:problem is that tx_outclock is generated differently in single-bank and "wide" SERDES. SERDES IP editor doesn't know about final implementation, thus it accpects tx_outclock phaseshifts that are only applicable in single bank design.

A separate pair of PLL outputs drives tx_outclock SERDES channel through dedicated "phase_shifted_tx_outclock_serdes.outclock_tree". In wide SERDES topology, the phase shifted outclock is apparently not available or not used for some reason. You can only implement phase shift values that are aligned with regular bit clock, e.g. 180° for frequency factor 2.

SERDES IP editor should issue a warning about possible phase shift implementation issues.

[lambert_yu]

SERDES IP editor should issue a warning about possible phase shift implementation issues.

Your advice is very well. Now there's no this warning message.

A separate pair of PLL outputs drives tx_outclock SERDES channel through dedicated "phase_shifted_tx_outclock_serdes.outclock_tree". In wide SERDES topology, the phase shifted outclock is apparently not available or not used for some reason. You can only implement phase shift values that are aligned with regular bit clock, e.g. 180° for frequency factor 2.

  Where could I find this content ?  Or just internal use?