How could I understand “IOPLL could drive the lvds tx transmitter in adjacent bank"

[lambert_yu]

Hi,

   In the "arria 10 Core Fabric and General purpose I/O handbook ":

   There 's one sentence "For differential transmitters, the PLL can drive the differential transmitter channels in its own I/O bank and adjacent I/O banks". And I followed this to build one design as below:

    1. refclk : refclk_0p from 2F bank

    2. IOPLL :  use internal pll in lvds IP configuration

    3.  tx transmitter: one channle in 2F bank, 4 channel in 2G bank (they are all not continous)

    4. output the txclk_out

   When I compiled the design, there's fitter error  Error(14566), Error (175006).

   I don't know where's error? Will I need to modify some part to complete this design?

   maybe :

   Solution 1: modify item2, use the external PLL?

   Solution 2 : only use the IOPLL, refclk, lvds tx transmitter in the same bank.

   Could someone help me about this?

Best Regards,

Lambert

[FvM]

I see the SERDES implementation details in post-mapping netlist viewer.

[lambert_yu]

Got it! Thanks! I think the root cause is the phase adjustment in this use case.