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Altera_Forum
Honored Contributor I
1,598 Views

How do access the converted MAX 10 ADC results?

Hi, 

 

I'm really new to the whole FPGA world and try to evaluate the MAX10 ADC as part of my thesis, but whatever I do I can't get it to work as I think it should. 

 

What I'm trying to do is, that I've got the MAX 10 FPGA Development board with the 10M50 and I want to read the Analog-in from Chanel 6 from ADC1 where a potentiometer is connected and in respect to the converted value I want to change the duty cycle of a PWM which controls one of the on board User LEDs. 

 

So far I've found a lot tutorials about the ADC but none where the converted values are processed and used further on. Most of the tutorials I saw just show the ADC to JTAG bridge, what doesn't help me at all. 

So basically to sum things up my main problem is that I don't know how to get and use the converted results. 

 

I would be really glad for any help, even a link or just anything would help. I'm kinda losing my mind over this. 

 

Thanks in advance. 

 

% --[ edit ] --- 

 

So just to clarify, what do I know. 

 

The MAX10 10M50 comes with a dual ADC with each 8 + 1 TSD input, with a 64 channel sequencer. 

It works like a regular 12bit SAR ADC with 1 MSPS for each ADC-"Core". 

For example a regular cycle would start that the inputs get sampled in order to the defined sequence and converted and at last stored in the sample storage or avalon ram. 

I know I need a PLL and what a PLL is to create the 10Mhz ADC input Clock. 

What don't know is how to access the sample storage or avalon ram to get to the converted results.
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8 Replies
Altera_Forum
Honored Contributor I
153 Views

Have you checked out these online trainings: 

 

https://www.altera.com/support/training/catalog.html?coursetype=online&language=english&keywords=adc 

 

You can use the ADC toolkit or store samples in on-chip memory for access through the Avalon slave interface. You can also set the IP up to offload the data off-chip. It depends on your options in the IP Parameter Editor. The Implementation training gives details on these options. 

 

If you're not familiar with the Avalon interface, there are other training classes available on it and Qsys.
Altera_Forum
Honored Contributor I
153 Views

Hi, yes I did but they don't really help me. I know how to implement an adc in qsys but I can use the adctoolkit but oder which IP can I use to acess the sampled values?

Altera_Forum
Honored Contributor I
153 Views

Again, it would have to be your own design to access the memory mapped locations. You can export the data out of Qsys if you want. Using the ADC toolkit is the easiest way. It depends on what you want to do in your design.

Altera_Forum
Honored Contributor I
153 Views

Sorry for my misunderstanding and maybe dumness, but I thought that adc toolkit is as mentioned in the Adc usermanual just a tool to check your qsys-design / adc for generell function.  

 

I'm not really getting where can I find the specific registers for my sampled values and how to access those in the Avalon storage. Because I thought I've to these ipblocks with qsys and Code my own verilogblocks and connect them in the "schematic". 

 

What I know is that there are these ADC_SAMPLE registers from 0x3F-0x00 for the 64 sequencer / samplestorage slots  

 

 

Is there an example of verilog code on how to access adc 1 samplestorage 1 register?
Altera_Forum
Honored Contributor I
153 Views

Did you ever get this problem solved? I am trying to do the same thing and the available documentation is not getting me there. I want to control the ADC and access the data with my custom verilog files. I have the ADC in my schematic, connected to 10 MHz clock from PLL c0. I am trying to start the ADC by writing to the sequencer control register (setting bit 0 high), then trying to read the results from the address store registers. I'm getting nothing; not sure if I'm doing it right. I'm assuming that the read & write lines are active high, and the clk line requires a pulse to latch the commands and results. Thanks.

Altera_Forum
Honored Contributor I
153 Views

Hi, Yes, I did after I had two meetings with some altera / Intel fae, which was informing but for the problem worthless, because they explained to me that I need use the nios2softcore for accessing the internal sample-storage and I don't wanted to use the nios.  

 

So what I did I used this tutorial --> http://www.alterawiki.com/wiki/bemicro_max_10#adc_finger_temperature_.28fingertemp.29_tutorial  

And modified their state machine for a custom sample storage. 

Maybe this helps you.
HKwon8
Beginner
153 Views

I'm suffering from same problem and i can't understand how to receive converted 12 bit digital data. Moreover, I thought your link will be 'a' clue to solve this problem but connection error. Could you help me?? I feel kinda losing my mind

dsc555
Beginner
133 Views

I found an updated link that has the "finger temperature example" you probably looking for:

https://community.intel.com/t5/FPGA-Wiki/BeMicro-Max-10/ta-p/735231

 

Hope this helps some people!