How many different frame can a F-Tile Ethernet IP output in one beat in segment interface?

[myrfy001]

Hi, from the PDF document, It says that a 400Gbps Ethernet controller can use segment interface, new frame can start at 8-Byte aligned position. 

My question is, how many ethernet frames can occur in a single beat on the 1024 bit segment interface?

First, to my understanding, for example, suppose the ethernet packet is at least 64 Bytes, so one beat may have data from 3 different ethernet frame (a 32 Byte tail part of the first frame, a 64 Byte whole frame, and a 32 Byte header part of next frame), is that correct?

Second, if the IP received broken frames(for example, a ethernet frame with just 32 bytes), will the IP output more frames in a single beat?

And can we set the max segment count in a single beat?

[ZiYing_Intel]

Hi,

We sincerely apologize for the inconvenience caused by the delay in addressing your Forum queries. Due to an unexpected back-end issue in our system, your Forum case, did not reach us as intended. As a result, we have a backlog of cases that we are currently working through.

Please be assured that we are doing everything we can to resolve this as quickly as possible. This will take some time, and we appreciate your patience and understanding during this period of time. Your case will be attended by AE soonest possible.

Thank you again for your patience and understanding, and we are committed to provide you with the best possible support.

Best regards,

zying

[ZiYing_Intel]

Hi,

If the minimum Ethernet frame size (excluding preamble and SFD) is 64 bytes, you could theoretically have one full minimum-sized frame and parts of two other frames within a single 1024-bit segment.

For example, you could have:

• A 32-byte tail of the first frame
• A 64-byte complete minimum-sized frame
• A 32-byte header of the next frame

If the IP does output broken frames, the number of frames in a single beat could potentially increase since broken frames are smaller than the minimum size. However, this would be an error condition, and the frames would not be valid Ethernet frames.

For instance, if the IP were to output 32-byte broken frames without discarding them, you could have up to four such frames in a single 1024-bit beat. But again, this would be an error scenario, and typically, Ethernet controllers are designed to handle errors according to the Ethernet standard, which would involve discarding frames that do not meet the minimum size requirement.

The behavior can vary significantly between different implementations, and the IP vendor's documentation will provide the most accurate and relevant information for your situation.

Best regards,

zying

[ZiYing_Intel]

Hi,

Do you still have any question about the case?

Best regards,

zying

[myrfy001]

Thanks. Your answer is almost the same as my assumption. But I want to know the answer that you mentioned "IP vendor's documentation will provide the most accurate and relevant information", I have read almost the whole document, but I don't have find out the accurate description about the behavior for RTile IP.

[ZiYing_Intel]

Hi,

Currently we don't have the R-tile Ethernet IP but we have the R-tile PCIe. For further information about the R-tile PCIe, you may refer to the link below https://www.intel.com/content/www/us/en/products/details/fpga/intellectual-property/interface-protocols/pcie-r-tile-hard-ip.html

Best regards,

zying

[ZiYing_Intel]

Hi,

Do you still have any question about the case?

Best regards,

zying

[ZiYing_Intel]

Hi,

Since no hear any feedback from you, I am now close the case. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread.

Best regards,

zying