How should I connect clk and pll_refclk0 in RapidIO IP Core of Arria10?

[SYiwe]

Hi all,

In my design I instantiate a RapidIO core and a ATX PLL core, and the device is Arria10.

clk is the reference clock for RX CDR block in transceiver,

pll_refclk0 is the input clock of ATX PLL,

clk and pll_refclk0 should be driven from the same clock source.

Is clk a differential signal?

Should I connect both of them to the same dedicated reference clock pin?

Thanks, regards.

[SreekumarR_G_Intel]

Hello , I would say connect to the external clock input to the global clock pin and add the clock constraint. Make sure it is connected to the non-inverted (name_p) clock if it is single ended clock input and inverted pin can be left open. Thank you , Regards, Sree