How to Configure Cyclone IV to LVDS Clock Inputs

[Altera_Forum]

Hi, I would like to know how to configure my Cyclone IV design project for LVDS clock inputs. Usually the system clocks are single-ended inputs, but in my new design my system clocks are differential.  

 I've tried using the Assignment Editor property to assign CKN/CK to the input port symbol pin but after I compile the project and then back annotate it assigns the input port symbol pin to a signal-ended clock pin not to a differential pair pins.  If anyone can help I would greatly appreciate it.  Thanks, joe

[Altera_Forum]

You need to set the I/O standard of the P side of the differential signal to LVDS. Quartus will then automatically assign the N side. 

 Cheers, Dave

[Altera_Forum]

I just figured it out. It is in the Pin Planner. Thanks!

[Altera_Forum]

You can also use a Tcl constraint. 

 If the clock pin has an internal termination, you also need to set the termination constraint to "OCT 100 OHMS" (or whatever its called for a Cyclone IV. This is the Stratix IV name).  Cheers, Dave

[Altera_Forum]

--- Quote Start ---  If the clock pin has an internal termination  --- Quote End ---   There's no differential OCT feature with Cyclone - Cyclone IV.

[Altera_Forum]

--- Quote Start ---  There's no differential OCT feature with Cyclone - Cyclone IV.  --- Quote End ---  Indeed :)  On page 114 of the Cyclone IV handbook PDF, Table 6-2, shows that there are no LVDS terminations.   C'mon Altera, how cheap!  Thanks for the pointer Frank. I'm thinking of using a Cyclone IV GX as a PCIe bridge in my next design.  Cheers, Dave