I am looking to disable the optimization done when multiplying by a constant. I have DSP blocks available that I want to reuse instead of having the operation mapped to logic. I am using Quartus II 15.0.
All to no avail. Any help is appreciated. Thanks!
If the block is written to be fully general at the Verilog/VHDL level, why do you care that in a particular instance, when you feed it constants, that Quartus does implementation optimization? Each time you instantiate the block, Quartus will look at all the inputs/outputs, and if inputs are constants, it will optimize around that. And for unused outputs the logic will be discared (by default, can be suppressed). Why do you care if Quartus is doing this?