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How to add a delay - Time digital converter (TDC) - begginer

Eric_truite
Beginner
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Hello everyone,

I'm using a DE0 Nano SoC, and I have a PLL that provides me with a frequency of 500 MHz. I want to generate pulse bursts on my GPIO connector. So far, I can create pulses with a duration of 2n, and everything works very well. The issue is that with a frequency of 500 MHz, I can only shift my signal every 2 ns.

Therefore, I would like to implement a Time Digital Converter (TDC) to add a delay and be able to shift the signal by 250 ps and/or 500 ps and/or 1 ns. Actually, the precision of the timing doesn't matter much. What I want to understand is the methodology, how it's done.

I've seen in publications and elsewhere that there are two steps. The first is to create this delay chain, using code? A drawing in Quartus?

The second step is to manually place the "blocks" in chip planner. It seems to me that we can simply drag and drop these blocks, and the goal is to put them in series to control the delay. But how do we understand these blocks? They are quite complicated.

Also, from what I've seen elsewhere, our counterparts use carry4. Do we have an equivalent?


Figure 1 : what I want to do (is this correct?)

Eric_truite_2-1709802806923.png

 

Figure 2 : Devil block

Eric_truite_1-1709802784809.png
Last thing: can we observe this delay in simulation? What interests me is solely the measurement on the GPIO connector, but I don't always have the metrology with me, whereas a computer does.
 
Thank you for reading.
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FvM
Valued Contributor III
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Core clock is limited to 500 MHz, but you can generate higher resolution time shifts with phase shifted PLL clock, fixed or dynamically varied with delay step down to 125 ps (1/8 of PLL VCO period).

I have used it e.g. for high resolution PWM, time-equivalent sampling and soft CDR.

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Eric_truite
Beginner
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Thank you for providing another method; I will go online to see what it entails. If you have more information, especially on how to accomplish this, for a PLL it's very simple, with 2 clicks Quartus does it for us. What about this implementation of the phase-shifted PLL clock? Nonetheless, I still want to understand how to make this TDC, for myself and for others in the future.

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FvM
Valued Contributor III
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Here's a Cyclone III delayline example, achieving about 400 ps per stage. You see a larger step after 16 stages when crossing a LAB boundary.
The delay is periodically stepped, recorded with infinite persistence.

delayline.gif

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TingJiangT_Intel
Employee
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We can insert LUTs along the signal path to control the delay, but this operation is highly dependent on the location of the LUT and cannot generate precise delays.


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Eric_truite
Beginner
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Indeed, that's what I'd like to do. I'll come back here with the solution when I have it.

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TingJiangT_Intel
Employee
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Great, if there is any updates please let us know.


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TingJiangT_Intel
Employee
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Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.


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