How to assign input clocks to the right pins in the Cyclone V GX FPGA

[t_alars]

Hello All,

After finishing my top level design, I got a task to find the right pin for each input clock I have.

I have never done this before and I read online, there is no a specific answer, but I need to learn to general strategy to find the right pins for the input clock I have

In my top Level I have 4 input clocks

1. PCIe input 100 MHz

2. PLL input 33 MHz

3. Flashconfig input 24 MHz

4. CPCI input 33 MHz

I have 2 questions:

A. How can I know which pin is suitable for a specific input clock? And for input clock to a PLL do I need to consider a certain case, or it is just like any input clock? How can I find the right pin to input the clock for each IP in different banks. Do I need to consider the FPGA banks in the assignment as well? Is pin planner tool would help me find the right pins I need?

B. In case I have 33 MHz input clock and I want this clock to be input to a PLL also to another IP (e.g SPI master), is this a save case? Or how can I handle such a case?

Taha

[sstrell · Accepted solution]

A.  Use the Pin Planner.  The Pin Planner identifies dedicated clock input pins with a little clock icon on the pin.  If you then add a PLL to your design, the Fitter should choose an appropriate PLL based on the input pin you've assigned the reference clock to.

B.  It might be better to mirror the 33 MHz clock on an output of the PLL before sending it to other IP.  That way you'll have matching clock delay through the PLL.

[AqidAyman_Intel]

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