How to assign the VREF pin?

[Altera_Forum]

Hi, 

I use ddr-core v7.2 sp3 in my design. It assigns dq, dqs, dm pins in bank6. I set other ddr pins in bank5. After compilation I check the pin-out file and find that VREF pins of bank6 are set as reference pin, but that of bank5 are set to unsed and driven to GND. Should I set some assignments to these pins? Thank you and forgive my poor english :).

[Altera_Forum]

Well, Quartus decides not to use the VREF pins of bank 5. So I would assume that none of the pins of bank 5 use SSTL. Maybe you could check that the pins associated to the DDR memory and located in bank 5 are set to the proper I/O level.

[Altera_Forum]

I did set the pins associated with ddr to SSTL-2 Class I in bank 5. :(

[Altera_Forum]

file:///C:/DOCUME%7E1/zhangt/LOCALS%7E1/Temp/moz-screenshot.jpg my assignments. 

https://www.alteraforum.com/forum/attachment.php?attachmentid=752

[Altera_Forum]

Vref is used by SSTL inputs and bidirectional pins only. You seem to have only outputs in bank 5. However, you should the pins connect according to the Quartus pinout file in case of doubt.

[Altera_Forum]

--- Quote Start ---  Vref is used by SSTL inputs and bidirectional pins only. You seem to have only outputs in bank 5. However, you should the pins connect according to the Quartus pinout file in case of doubt.  --- Quote End ---   Thank you very much. I have connected these vref pins to reference voltage:(. Now I set the unused pins as input tri-stated to see whether the ddr can work.