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How to build a carry-chain in Quartus II fitter instead of using LUTs?

kgrcfff
Beginner
1,096 Views

Hello everyone,

  I have a question about using Quartus II fitter to build a carry-chain.  Specifically, I want to ensure that the fitter uses a real adder circuit instead of using LUTs during the layout process.

 

Here is my verilog:

module Tfine_IP3(input clk_50M,
input start,
output clk,
output Sample_clk,
output clk_trig,
output [282:0]th_code/*synthesis keep*/);
wire [282:0]cout;
wire [282:0]w;

add a0(.dataa(1'b1),.datab(1'b0),.cin(start),.result(th_code[0]),.cout(cout[0]));

add a1(.dataa(1'b1),.datab(1'b0),.cin(cout[0]),.result(th_code[1]),.cout(cout[1]));
add a2(.dataa(1'b1),.datab(1'b0),.cin(cout[1]),.result(th_code[2]),.cout(cout[2]));
add a3(.dataa(1'b1),.datab(1'b0),.cin(cout[2]),.result(th_code[3]),.cout(cout[3]));
endmodule

 

adder settings

kgrcfff_0-1682578401578.png

kgrcfff_1-1682578419326.png

 

RTL viewer (implement by carry-chain):

kgrcfff_3-1682578539650.png

Technology map viewer(implement by LUT):

kgrcfff_2-1682578513124.png

 

  I have been trying to find a way to force the Quartus II fitter to use an adder circuit during layout, but have not had much success.  I searched advanced setting(Fitter) for a long time but to find a proper way to implement the carry-chain.  Can anyone provide me with some guidance or tips on how to accomplish this?

I am using Quartus II version [quartus ii 18.1 lite edition], and any help would be greatly appreciated.

Thank you in advance!

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1 Solution
ShengN_Intel
Employee
1,056 Views

Hi,

 

In the verilog code, I think you have to connect dataa and datab to input ports instead of constant 1'b1 / 1'b0. If connect to input ports you'll get map viewer result like below pic:

Screenshot 2023-04-28 164408.png

For example, taking single lpm_add_sub megafunction original map viewer result, the result like pic below:

lpm_add_sub_map.png

If connect  lpm_add_sub megafunction dataa and datab to constant, you'll get the result like below pic instead:

constant.pngconstant_map.png

Thanks,

Best Regards,

Sheng

p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.

 

View solution in original post

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3 Replies
FvM
Valued Contributor III
1,081 Views
Hello,
I think there are two problems with your experimental code.
1. lpm_add_sub is an adder macro, not a LAB low-level primitive. It's processed as input to the synthesis tool, not directly inferring logic array blocks.
2. By feeding all adder inputs except carry with constants, Quartus will be most certainly blocked from using arithmetic mode and not use carry chain.

I wonder what you want to achieve with the design? Create a delay line?

The best way to make Quartus use the carry chain is to design a problem that is recognized as arithmetic.

Regards,
Frank
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ShengN_Intel
Employee
1,057 Views

Hi,

 

In the verilog code, I think you have to connect dataa and datab to input ports instead of constant 1'b1 / 1'b0. If connect to input ports you'll get map viewer result like below pic:

Screenshot 2023-04-28 164408.png

For example, taking single lpm_add_sub megafunction original map viewer result, the result like pic below:

lpm_add_sub_map.png

If connect  lpm_add_sub megafunction dataa and datab to constant, you'll get the result like below pic instead:

constant.pngconstant_map.png

Thanks,

Best Regards,

Sheng

p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.

 

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kgrcfff
Beginner
963 Views

Hello,

Thank you for such a detailed answer. Through these methods I have solved my problem. Thank you again.

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