How to choose device : CPLD or FPGA ?

[Altera_Forum]

I want to implement a polynomial function to continuously process a digital temperature signal and output a variable based on such evaluation. What device to look out for ? CPLD or FPGA ?  

How can I decide that this implementation would need this much LEs ?  Please help in this regard.

[Altera_Forum]

CPLDs are very small devices with no dedicated internal rams or multipliers. FPGAs have internal rams and multipliers. CPLDs are very cheap, FPGAs range from cheap to very expensive. 

 So if you know its a very simple design with no need for any serious maths or storage, stick with a CPLD. Otherwise you will need an FPGA.  As for estimating your LEs, best way is to write the source code and compile it. estimating LEs for designs more complicated than a few gates is dufficult. On the other hand it can be easy to estimate memory and multiplier requirements.

[Altera_Forum]

Thanks Tricky. 

My polynomial equation is of 3rd order and I need to process only one input signal.

[Altera_Forum]

In that case, you'll probably need multipliers. They can be done without dedicated multipliers but you need as many adders per multiplier as you have bits. 

 If that is all it is you might be able to squeeze it into a large CPLD, but it might be easiest to go with an FPGA. Also, try not to do division on either CPLD or FPGA, its much easier to multiply by 1/n rather than divide by n.  Thirdly, if you're thinking about floating point, try changing everything to fixed point. FPGAs dont like floating point and you would really struggle on CPLDs.

[Altera_Forum]

Thanks Tricky for your valuable suggestions.

[Altera_Forum]

Considering  

Y = Ax3 + bx2 + Cx + D I conclude at 5 multipliers and 3 adders ( using both mul. and add.) or  43 addres ( using only adders, for a 8 bit input)  It can give a rough estimate of LEs consumed ?

[Altera_Forum]

it wont be as simple as 43 adders 

 if x is 8 bits, x^2 will need 16 bits, and x^3 needs 24. Then if A,B,C,D are 8 bits again, the output is going to be 32 bits.  So thats a lot of adders. Different devices have different size LEs - some have 4input LUTs, some have 6. So to estimate the number of LEs required its simpler just to write the code and compile it.

[Altera_Forum]

It can be done with 38 adders or in total about 1000 'full adders', which comes down to about 1000 LE's for a MAXII device (assuming a few AND-ing functions can be combined at the same time), requiring a EPM1270 device, so you're better off using the smallest of Cyclone II, III or IV series and just use the hardware multipliers.

[Altera_Forum]

Pipe-line the multiplication. You can multiply + accumulate. A MAX II device should do it.

[Altera_Forum]

--- Quote Start ---  Pipe-line the multiplication. You can multiply + accumulate. A MAX II device should do it.  --- Quote End ---   You mean 'serialise it'. Pipe-lining increases speed but doesn't decrease the amount of LUTs. A 32 by 8 serial multiply takes about 190 Logic Cells in MaxII. This is some 'old' AHDL code I did many years ago, I guess it can be improved upon though. paawansharmas didn't indicate how fast he needs to run.

[Altera_Forum]

I intend to use a fast ( bare ) thermocouple whose response time is 0.3 sec, such that the entire calculation wouldn't cross 0.5 seconds in giving output.

[Altera_Forum]

--- Quote Start ---  I intend to use a fast ( bare ) thermocouple whose response time is 0.3 sec, such that the entire calculation wouldn't cross 0.5 seconds in giving output.  --- Quote End ---   At speed you also have other options than a CPLD or FPGA ...

[Altera_Forum]

Yes, I meant that.

[Altera_Forum]

Well , I think of going ahead with MAX V CPLD having 570 LEs. 

Board cost is also very cheap.