How to clock this Tranceivers based design?

[Altera_Forum]

Hi all, 

 I need to make some communication device and I want to check if this is possible with the Altera chips and the Tranceivers. I studied different UserGuides, but I still not sure how to clock the different parts.  The problem:  I need one main controller that runs at 150Mc. It needs to control 3 or 4 Tranceivers. For the receive side I do not see a real problem. It is about the transmit side. Each Tranceiver must be dynamical configurable to operate at 3Gb/s, 1.5Gb/s or 750Mb/s. So the TX Phase Compensation Fifo has to be written with 150MHz, 75MHz or 37.5MHz (20 bits per clock).   How can I clock the TX Phase Compensation fifo with one of these tree clocks (dynamically switchable)? If the Transmit PLL uses the 150MHz as source to make the line-rate clocks, then the rate at which the TX Phase Compensation fifo is read is also synchronous to this clock. So when I use the 150MHz clock (or a divided 75MHz or 37.5MHz) to write the fifo, I will be frequency syncrhonous. But the phase relation is unknown. Does the TX Phase Compensation fifo tollerate all kinds of phase differences, without knowing the relastion in advance? Do I have to start the fifo in same special way to make shure it is filled to the correct level?  I appriciate very much if somebody can advise me or point me into the right direction.  thanks

[Altera_Forum]

Could you reveal a little more about what you are trying to do? What exactly is it your transmitting / receiving? 

 1 - Phase compensation FIFO will compensate for any phase mismatch but will not compensate for frequency mismatch. You don't really need to configure anything special for this. The FIFO will be initialized on reset.  2 - On transmit, you could just oversample by 1X, 2X, and 4X respectively. This would make your life easier when it comes to clocking.  3 - The receive side may actually be more difficult than you think. You may need to do some dynamic reconfiguration of the receiver PLL to support the multiple data rates.  Jake

[Altera_Forum]

If your problem is how to clock the fifo then a simple solution is to use the 150MHz for all cases but switch a clock enable which will be high always for 150MHz, divided for the other two cases. I am sure your fifo will have clock enable port.

[Altera_Forum]

--- Quote Start ---  If your problem is how to clock the fifo then a simple solution is to use the 150MHz for all cases but switch a clock enable which will be high always for 150MHz, divided for the other two cases. I am sure your fifo will have clock enable port.  --- Quote End ---    Yes, I can do that for the fifo a need in the receive lane. But the clock input of the Tranceiver (the tx_coreclk) does not come with a enable input. So I will have to dynamical switch the clock between the 3 frequencies. Is that possible in an Altera FPGA?

[Altera_Forum]

The transceiver can by dynamically reconfigured to support the multiple clocking schemes you are trying to achieve.  

  Jake

[Altera_Forum]

--- Quote Start ---  Yes, I can do that for the fifo a need in the receive lane. But the clock input of the Tranceiver (the tx_coreclk) does not come with a enable input. So I will have to dynamical switch the clock between the 3 frequencies. Is that possible in an Altera FPGA?  --- Quote End ---    For coreclk I don't think you can do that. As stated by Jacobjones you can go for highest data rate and use oversampling on lower data rates to bring them to the high rate but discard the nonvalid data bits. Oversampling ave been discussed in some previous posts

[Altera_Forum]

--- Quote Start ---  The transceiver can by dynamically reconfigured to support the multiple clocking schemes you are trying to achieve.    Jake  --- Quote End ---    Hi Jake,  Can you please elaborate on this feature and which device supports it. Thanks.

[Altera_Forum]

--- Quote Start ---  If your problem is how to clock the fifo then a simple solution is to use the 150MHz for all cases but switch a clock enable which will be high always for 150MHz, divided for the other two cases. I am sure your fifo will have clock enable port.  --- Quote End ---    Yes, I can do that for the fifo that I need in the receive lane. But the clock input of the Tranceiver (the tx_coreclk) does not come with a enable input. So I will have to dynamical switch the clock between the 3 frequencies. Is that possible in an Altera FPGA?

[Altera_Forum]

Which FPGA are you planning on using? 

 For Stratix II GX. http://www.altera.com/literature/hb/stx2gx/stxiigx_sii5v2_01.pdf Read the section on Stratix II GX Dynamic Reconfiguration.  For Stratix IV GX. http://www.altera.com/literature/hb/stratix-iv/stx4_5v3.pdf