Hi All,I'm designing a FPGA project with cycloneIII. Since we have to use LVDS input together with DDR(SSTLII classI) and 2.5v LVCMOS voltage level I/O. the minimum pin distance between LVDS and 2.5v LVCMOS must be guaranteed. So I create a vacant module with all I/Os instantiated. My question is, is that ture that only if the compilaton can successfully pass that means the I/O assignment is ok? Anyone who have similar experience can give out some advice? Thanks !
--- Quote Start --- My question is, is that ture that only if the compilaton can successfully pass that means the I/O assignment is ok? --- Quote End --- If compilation includes fitter process then yes, it is true. A little tip: you can configure Quartus to check I/O assignments validity before full compilation is initiated. Go to Assignments->Settings->Compilation Process Settings and check "Run I/O assignment analysis before compilation". Or you can run this check directly from Processing->Start menu.