=== SHORT INTRO ===
Due to some questionable architecture decisions in the past, we ended up with a large circuit implemented in three related clock frequencies using timing division multiplexing. This FPGA firmware is replicated to 116 boards featuring the largest Arria 10 FPGA. This circuit is divided into three parts running at 320 MHz, 240 MHz, and 280 MHz (all multiples of 40 MHz), please see the attached photo of the clock topology.
=== CLOCK TOPOLOGY ===
A clock buffer drives a 160 MHz clock that feeds an Arria 10 IOPLL that outputs 160, 320, and 1200 MHz. The 320 MHz output is connected to a cascaded IOPLL through the adjpllin reference clock input to generate the 240 MHz clock. Again, the clock topology is very questionable but I can't change it right now, unfortunately.
=== ISSUE ===
There are hundreds of bits crossing between these three regions. Fortunately, we designed these transfers in such a way that the data stays constant for 25 ns before each inter-clock transfer. At the destination, the data are latched at a configurable phase.
For example, see the attached picture. The 320 MHz input serial stream (magenta) is deserialized to a 320 MHz parallel word that changes every 25 ns, i.e. every 8 clock cycles (yellow), then it is latched by a register running at 240 MHz (orange). The clock enable of the register indicated in orange is asserted one clock cycle every 25 ns, i.e. one time every 6 clock cycles of 240 MHz. The phase of this periodic clock_enable signal can be selected from the 6 discrete possible values using a multiplexer connected to a shift register holding the 6 different signal phases.
One can notice that despite the fact that source and destination registers are running at 320 MHz and 240 MHz, the data are refreshed every 40 MHz cycles. When one takes into account the fact that the clock enable is asserted periodically only once at 25 ns at both ends, one can consider this transfer very similar to a 40 MHz intra-clock transfer. However, without a suitable timing constraint, the STA tool is unable to guess this information.
=== QUESTIONS ===
1) What is the right constraint for this 320-to-240 MHz transfer which both clocks enable are asserted only once every 40 MHz cycle?
2) Currently I am latching the destination register at the middle of the 25 ns window of the source register. Is this the best phase offset for such a transfer?
3) By default Quartus considers the default relationship for this transfer to be 0.001 ns, i.e. 1 ps. I don't quite understand how Quartus ended up with this 1 ps default setup relationship. Would you know how to explain this?
Link Copied
