SFL problem

[sda1902]

Hi !

In my project, I planned to use SFL  to access the configuration flash, which was planned to contain not only the configuration, but also the data.
Problem:
The SFL project loads into the FPGA via JTAG without errors, but does not work. I remove the SFL module from the project and the project works.
Shortened SFL instance to

sfl SFL(.noe_in(0));

and still the project does not work. If I remove the module declaration, the project works.
If I write the project to the configuration flash using a jic file and reboot FPGA from Flash (AS configuration mode), it will still not work if there is an SFL module in it.
This behavior is observed on Cyclone 5 and Arria 5.

Question:
What am I doing wrong ? Maybe I need to add some assignments or change the project or device settings?

[Fakhrul]

Hi sda1902,

My apologies I may have overlooked this post. Here a few item you may need to check:

1. Instantiate SFL IP Core Correctly:

• Ensure proper instantiation in the top-level design to connect JTAG and ASMI hard logic.

1. Set Configuration Signals:

• Set noe_in to 0 to enable the SFL IP core. If not accessing ASMI externally, tie this signal to GND.

1. JTAG to AS Bridge:

• Load the SFL image to bridge JTAG to the ASMI interface, crucial for programming via JTAG-ASMI.

1. Shared ASMI Interface:

• Enable Share ASMI interface if sharing the ASMI interface in your design.

1. Enhanced Mode SFL:

• Ensure Use enhanced mode SFL is appropriately set. For Cyclone V and Arria V devices, this parameter must be enabled.

1. Programming Flow:

• After programming, reconfigure the FPGA by cycling the nConfig pin.

For further details, please refer to the provided document - AN 370: Using the Intel FPGA Serial Flash Loader.

Regards,

Fakhrul

[Fakhrul]

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