reconfig PLL IP do not respond to user logic

[Allan6]

Hi Intel Community,

I'm working on a project involving dynamic PLL reconfiguration using Altera/Intel PLL and PLL Reconfig IP cores in a Cyclone V FPGA. I've followed the steps outlined in the PLL Reconfig documentation, but my PLL reconfig does not seem to respond to my controller logic.

Setup Details:

FPGA Device: Cyclone V
Intel Quartus Prime Version: 18.1
PLL IP Core: Intel FPGA PLL
PLL Reconfig IP Core: Intel FPGA PLL Reconfig

Steps Implemented:

• Generated PLL and PLL Reconfig IP cores.
• Connected the reconfig_to_pll and reconfig_from_pll buses between the PLL Reconfig and PLL instances.
• Implemented the state machine for dynamic reconfiguration.
• Use Modelsim to verify the result but PLL and PLL Reconfig have no value.

and my control logic behavior match from the PLL Reconfig doc

I also attached my testbench and vhdl files below 

Any help or pointers would be greatly appreciated!

Thank you in advance!

[AqidAyman_Intel]

Hello,

Apologize for the delay response.

Let me try to follow your steps and see if can reproduce the same issue from my side and report to you back.

Appreciate your patience.

[Allan6]

Hello,

No problem at all. I appreciate your follow-up. Have you had a chance to try the steps I mentioned earlier? Were you able to reproduce the issue on your side?

Please let me know if you have any progress or need further information from me.

[AqidAyman_Intel]

Hi,

I really apologies as I am having difficulty reproducing the issue that you are facing.

However, I found this article that might be able to help you:

https://www.intel.com/content/www/us/en/support/programmable/articles/000079377.html?wapkw=Intel%20FPGA%20PLL%20Reconfig

[Allan6]

Hi,

Thank you for the replay

So  I does that mean you have a working project if that is the case can you send me the project you have

Thank you for the assistance