I have questions on how to capture source-synchronous DDR (DDIO) data into the Stratix-10 FPGA on the LVDS I/O Banks. We are currently using the 1SX280HU2F50E1VGAS H-Tile device on the Stratix 10 SoC Dev Kit. Later we will use the L-Tile part.
I am designing a high-speed interface to a camera image sensor. The image sensor transmits 48 channels of sub-LVDS pixel data, along with the LVDS DDR clock. The pixel data is captured at DDR speeds (data is captured on both the rising and falling edge of the LVDS DDR clock). The DDR clock runs at 480MHz, and the pixel data is captured at 980Mbps.
I read both the Intel Stratix 10 High-Speed LVDS I/O User Guide v2020.01.08 (LVDS UG), and the Intel Stratix 10 General Purpose I/O User Guide v2020.01.03 (GPIO UG) to determine how to perform DDR data capture using the LVDS I/O Banks.
The LVDS UG, on page 16, stated “You can bypass the deserializer to support DDR (x2) and SDR (x1) operations. The deserializer bypass is supported through the GPIO IO Core.” Based on that, I started a design with the GPIO IP Core, following the GPIO UG.
I set up my design to use the GPIO IP Core in the DDIO Mode with Half-Rate conversion, as described on page 49 of the GPIO UG. I started my design in Platform Designer. I set up and configured the GPIO IP Core in the DDIO register mode with half-rate logic, as shown in the screen-shot below:
This is where I discovered the Quartus Prime Pro message: “Intel GPIO supports a maximum interface frequency of 300 MHz”. This limitation was not stated anywhere in the GPIO UG, nor did I see it in the Stratix 10 datasheet. My design requires an interface frequency of 480MHz to interface with the image sensor, but the GPIO IP core is limited to 300MHz.
I went back and reread the LVDS UG to see how to implement an LVDS DDR receiver design, but it is unclear to me on how do this.
My question is: How to create an LVDS DDR receiver design in the Stratix 10 with an interface frequency of 480MHz?
Thanks very much for any help or pointers.
I see your point. Based on the datasheet Table 36, Receiver section, J=1 or J=2 for DDR...and then referring to footnote 66...basically what it means is that how fast you can receive data depends on how good you are at closing timing.
It seems what the datasheet and GPIO IP warning message does not agree with each other.
Let me check and see.
Updating you on my findings.
1) LVDS SERDES IP does not support x2 (DDR), to do so you need to use GPIO IP.
2) The datasheet footnote 66 is suggesting that there could be signal integrity or board skews that could cap the maximum frequency.
3) From (2), even if you have a perfect signal integrity, the maximum frequency you can achieve is 300MHz (as what the Quartus indicated).
4) I tried to check for alternative using the XCVR, but XCVR does not support DDR and XCVR has other limitations with it as well (coupling, run length, etc), which may further complicate things.
Thank you for researching the DDR receiver design for the Stratix 10 FPGA. It is good to know that I need to stay with the GPIO IP and limit DDR transfer speed to 300MHz, best case.
I discussed this with our System Engineer, and he will adjust the system requirements for the lower speed. I will work on the design and see what throughput can be achieved.