How to deal with this warning?

[Altera_Forum]

Hi Dears: 

  I am using EPM7256ATEC144 to do some logics. There is a warning after compilating. This warning is below:  "Warning: Macrocell buffer inserted after node "true_trig_in[12]""   So the tpd of "true_trig_in[12]" is one gate delay bigger than the others same kind paths. And this warning may appear in differ path when there is different compilations, such as it can change to appear on "true_trig_in[21]" when differ compilating.  But this warning disappears when I implemented this logic in EPM7512AETC144.  The bus trug_trig_in get same tpd ( or logic delay) is very important for this project. Please help me on this issue. Thanks!!!

[Altera_Forum]

Is there nobody encounter this issue?????????????!

[Altera_Forum]

It seems the pins configuration caused this issue. Because there isn't this issue when I didn't configure the pins and the QII auto configure the pins. 

 If it's right, we must change the hardware. Can anybody tell me how to deal with this issue without change our hardware?

[Altera_Forum]

Can you add a macrocell buffer to the other paths too? 

 it looks like a 'pin locking' problem. No enough routing resources and a particular signal needs to pass through a macrocell in order to reach a particular pin.  Hope it helps.