How to define a variable and assign a variable

[Altera_Forum]

want to define and assign variable, however got error

when use variable

Error (10500): VHDL syntax error at LabT1.vhd(31) near text "variable"; expecting "end", or "(", or an identifier ("variable" is a reserved keyword), or a concurrent statement

when use generic

Error (10500): VHDL syntax error at LabT1.vhd(31) near text "generic"; expecting "end", or "(", or an identifier ("generic" is a reserved keyword), or a concurrent statement

other error

Error (10500): VHDL syntax error at LabT1.vhd(31) near text ":="; expecting ";", or "port", or "generic"

Error (10500): VHDL syntax error at LabT1.vhd(32) near text ":="; expecting ";", or "port", or "generic"

Error (10500): VHDL syntax error at LabT1.vhd(33) near text ":="; expecting ";", or "port", or "generic"

Error (10500): VHDL syntax error at LabT1.vhd(34) near text ":="; expecting ";", or "port", or "generic"

Error (10500): VHDL syntax error at LabT1.vhd(37) near text ":="; expecting ";", or "port", or "generic"

Error (10500): VHDL syntax error at LabT1.vhd(38) near text ":="; expecting ";", or "port", or "generic"

Error (10500): VHDL syntax error at LabT1.vhd(39) near text ":="; expecting ";", or "port", or "generic"

Error (10500): VHDL syntax error at LabT1.vhd(40) near text ":="; expecting ";", or "port", or "generic"

Error (10500): VHDL syntax error at LabT1.vhd(53) near text "<"; expecting "(", or an identifier, or unary operator

Error (10500): VHDL syntax error at LabT1.vhd(53) near text ";"; expecting "<="

Error (10500): VHDL syntax error at LabT1.vhd(54) near text ">"; expecting "(", or an identifier, or unary operator

Error (10500): VHDL syntax error at LabT1.vhd(55) near text ~

Error (10500): VHDL syntax error at LabT1.vhd(55) near text ">"; expecting "(", or an identifier, or unary operator

Error (10500): VHDL syntax error at LabT1.vhd(96) near text ":"; expecting ")", or ","

Error (10500): VHDL syntax error at LabT1.vhd(97) near text ":"; expecting ")", or ","

Error (10500): VHDL syntax error at LabT1.vhd(116) near text "/"; expecting "end", or "(", or an identifier, or a sequential statement

Error (10500): VHDL syntax error at LabT1.vhd(117) near text "/"; expecting "end", or "(", or an identifier, or a sequential statement

Error (10500): VHDL syntax error at LabT1.vhd(118) near text "/"; expecting "end", or "(", or an identifier, or a sequential statement

LIBRARY ieee;

USE ieee.std_logic_1164.all;

ENTITY LabT1 IS

PORT ( SW : IN STD_LOGIC_VECTOR(17 DOWNTO 0);

LEDR : OUT STD_LOGIC_VECTOR(17 DOWNTO 0);

--Input

CLOCK_50 : IN STD_LOGIC;

--ENET0_INT_N

--ENET0_LINK100

ENET0_RX_CLK : IN STD_LOGIC;

--ENET0_RX_COL

--ENET0_RX_CRS

ENET0_RX_DATA : IN STD_LOGIC_VECTOR(3 DOWNTO 0);

--ENET0_RX_DV

--ENET0_RX_ER

ENET0_TX_CLK : IN STD_LOGIC;

--Output

ENET0_GTX_CLK : OUT STD_LOGIC;

--ENET0_MDC

--ENET0_RST_N

ENET0_TX_DATA : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);

ENET0_TX_EN : OUT STD_LOGIC

--ENET0_TX_ER

);

END LabT1;

ARCHITECTURE Behavior OF LabT1 IS

BEGIN

variable IPsource_1 : integer := 192;

variable IPsource_2 : integer := 168;

variable IPsource_3 : integer := 0;

variable IPsource_4 : integer := 5;

--"IP destination" - put the IP of the PC you want to send to

variable IPdestination_1 : integer := 192;

variable IPdestination_2 : integer := 168;

variable IPdestination_3 : integer := 0;

variable IPdestination_4 : integer := 1;

--"Physical Address" - put the address of the PC you want to send to

--10-78-D2-AD-90-CB

variable PhysicalAddress_1 := X"10";

variable PhysicalAddress_2 := X"78";

variable PhysicalAddress_3 := X"D2";

variable PhysicalAddress_4 := X"AD";

variable PhysicalAddress_5 := X"90";

variable PhysicalAddress_6 := X"CB";

-- we send a UDP packet, 18 bytes payload

-- calculate the IP checksum, big-endian style

variable IPchecksum1 = X"0000C53F" + (IPsource_1<<8)+IPsource_2+(IPsource_3<<8)+IPsourc e_4+(IPdestination_1<<8)+IPdestination_2+(IPdestin ation_3<<8)+(IPdestination_4);

variable IPchecksum2 = ((IPchecksum1 & X"0000FFFF")+(IPchecksum1>>16));

variable IPchecksum3 = ~((IPchecksum2 & X"0000FFFF")+(IPchecksum2>>16));

--reg [6:0] rdaddress;

--reg [7:0] pkt_data;

tx_process : process(CLOCK_50)

begin

if SW(0) = '1' then

h00: ENET0_TX_DATA <= X"55";

h01: ENET0_TX_DATA <= X"55";

h02: ENET0_TX_DATA <= X"55";

h03: ENET0_TX_DATA <= X"55";

h04: ENET0_TX_DATA <= X"55";

h05: ENET0_TX_DATA <= X"55";

h06: ENET0_TX_DATA <= X"55";

h07: ENET0_TX_DATA <= X"D5";

--Ethernet header

h08: ENET0_TX_DATA <= PhysicalAddress_1;

h09: ENET0_TX_DATA <= PhysicalAddress_2;

h0A: ENET0_TX_DATA <= PhysicalAddress_3;

h0B: ENET0_TX_DATA <= PhysicalAddress_4;

h0C: ENET0_TX_DATA <= PhysicalAddress_5;

h0D: ENET0_TX_DATA <= PhysicalAddress_6;

h0E: ENET0_TX_DATA <= X"00";

h0F: ENET0_TX_DATA <= X"12";

h10: ENET0_TX_DATA <= X"34";

h11: ENET0_TX_DATA <= X"56";

h12: ENET0_TX_DATA <= X"78";

h13: ENET0_TX_DATA <= X"90";

--IP header

h14: ENET0_TX_DATA <= X"08";

h15: ENET0_TX_DATA <= X"00";

h16: ENET0_TX_DATA <= X"45";

h17: ENET0_TX_DATA <= X"00";

h18: ENET0_TX_DATA <= X"00";

h19: ENET0_TX_DATA <= X"2E";

h1A: ENET0_TX_DATA <= X"00";

h1B: ENET0_TX_DATA <= X"00";

h1C: ENET0_TX_DATA <= X"00";

h1D: ENET0_TX_DATA <= X"00";

h1E: ENET0_TX_DATA <= X"80";

h1F: ENET0_TX_DATA <= X"11";

h20: ENET0_TX_DATA <= IPchecksum3(15:8);

h21: ENET0_TX_DATA <= IPchecksum3(7:0);

h22: ENET0_TX_DATA <= IPsource_1;

h23: ENET0_TX_DATA <= IPsource_2;

h24: ENET0_TX_DATA <= IPsource_3;

h25: ENET0_TX_DATA <= IPsource_4;

h26: ENET0_TX_DATA <= IPdestination_1;

h27: ENET0_TX_DATA <= IPdestination_2;

h28: ENET0_TX_DATA <= IPdestination_3;

h29: ENET0_TX_DATA <= IPdestination_4;

--UDP header

h2A: ENET0_TX_DATA <= X"04";

h2B: ENET0_TX_DATA <= X"00";

h2C: ENET0_TX_DATA <= X"04";

h2D: ENET0_TX_DATA <= X"00";

h2E: ENET0_TX_DATA <= X"00";

h2F: ENET0_TX_DATA <= X"1A";

h30: ENET0_TX_DATA <= X"00";

h31: ENET0_TX_DATA <= X"00";

--payload

h32: ENET0_TX_DATA <= X"00"; // put here the data that you want to send

h33: ENET0_TX_DATA <= X"01"; // put here the data that you want to send

h34: ENET0_TX_DATA <= X"02"; // put here the data that you want to send

h35: ENET0_TX_DATA <= X"03"; // put here the data that you want to send

h36: ENET0_TX_DATA <= X"04"; // put here the data that you want to send

h37: ENET0_TX_DATA <= X"05"; // put here the data that you want to send

h38: ENET0_TX_DATA <= X"06"; // put here the data that you want to send

h39: ENET0_TX_DATA <= X"07"; // put here the data that you want to send

h3A: ENET0_TX_DATA <= X"08"; // put here the data that you want to send

h3B: ENET0_TX_DATA <= X"09"; // put here the data that you want to send

h3C: ENET0_TX_DATA <= X"0A"; // put here the data that you want to send

h3D: ENET0_TX_DATA <= X"0B"; // put here the data that you want to send

h3E: ENET0_TX_DATA <= X"0C"; // put here the data that you want to send

h3F: ENET0_TX_DATA <= X"0D"; // put here the data that you want to send

h40: ENET0_TX_DATA <= X"0E"; // put here the data that you want to send

h41: pkt_data <= X"0F"; // put here the data that you want to send

h42: pkt_data <= X"10"; // put here the data that you want to send

h43: pkt_data <= X"11"; // put here the data that you want to send

default: pkt_data <= X"00";

end if;

end process tx_process;

END Behavior;

[Altera_Forum]

Reviewing some of your posts, I get the impression that you are missing a good VHDL text book. 

 Various VHDL syntax errors in your text: - double begin in the architecture - declaration of regular variables outside a process or function - variable declaration without a type specification - using Verilog operators and comment syntax in VHDL - broken case construct

[Altera_Forum]

your guess is right, i have 4 books, 2 of them are using Verilog, 1 of them only teaching logic math, final 1 of them have examples but not have examples i need 

would you mind telling me how to fix it directly as i still do not know the correct syntax

[Altera_Forum]

As a general suggestion, you should use CONSTANT objects instead of variables. They can be defined in the declaration part of the architecture with arithmetic expressions. 

 An address counter to select data bytes for transmission is missing. You also can't send 8-Bit data to a 4-Bit transmit port.

[Altera_Forum]

which vhdl book is good? 

how to fix syntax <<, >> and ~? X"55" is 8bit, how to send 8bit data to 4bit port? i know counter, however, what is address counter?  i read verilog example that it use state to determine 8 bit to nibble, but where do this state connect with?