I am designing a PCB for an Arria 10 GX FPGA, and currently planning the power delivery network (PDN).
I am using the device specific PDN tool with an 10AX115H_F34 device. The default PDN configuration connects VCC, VCCP, and VCCERAM together and reports they collectively have 106 power/ground via pairs. This is the same as the total number of connected power pins.
However, these power pins are clustered in the center of the device, where there are relatively few GND pins. If I try to match up power and ground vias on a one-to-one basis, I can only find approximately 50 pairs due to the limited number of GND pins in this area.
What defines a "power/ground via pair" ?
Do the vias have to be adjacent? If so, does the adjacency have to be horizontal/vertical or does diagonal adjacency count?
For example, if there are eight power vias surrounding one ground via, how many power/ground via pairs are there?
Thanks for any help!
The power/GND via is basically the via between the power plane and the GND plane for each rail.
Please refer following link. It has very good explanation on how to place the vias. https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an574.pdf