How to do the timing constrain of the clolks of ALTCLKCTRL

[Altera_Forum]

I had instanced a ALTCLKCTRL IP core in my project .The ALTCLKCTRL IP core has two clocks input ports and one output ports, the one is 125MHz(inclk0),the other one is 48MHz(inclk1). So How can I do the timing constrain.

[Altera_Forum]

Using TimeQuest. Create a clock for each input clock (inclk0 & inclk1) with their respective frequencies. 

 Are you concerned this doesn't constrain what you want?  Cheers, Alex

[Altera_Forum]

What you suggested I have done. But the output clock has two different frequencies at the different Time Bucket. In my project ，there are two FIFOs.when the FIFO1 is full ,the rdclk of the FIFO1 changes from 125MHz to 48MHz, meanwhile ,the rdclk of the FIFO2 changes from 48MHz to 125MHz. The wrclk of the two FIFO is always 125MHz.

[Altera_Forum]

So the entire design needs to work at 125MHz. Quartus will (should) realise this if you constrain the clocks as you have. 

 Quartus can work out that the read side of each FIFO needs to operate at 125MHz (as well as 48MHz). TimeQuest will report timing against both 125MHz & 48MHz clocks. It's (perhaps) likely to meet timing at 48MHz. However, the same read side logic may not meet timing at 125MHz. TimeQuest will report timing for the read side logic against both source clocks.  Cheers, Alex

[Altera_Forum]

I have got it , thank you!